Data Sheet
ADP2165/ADP2166
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18
17
16
15
14
13
SYNC
RT
PVIN
SW
ADP2165/
ADP2166
SW
TRK
SS
TOP VIEW
SW
4
5
6
(Not to Scale)
COMP
FB
SW
PGND
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED
PAD TO AN EXTERNAL GROUND PLANE
UNDERNEATH THE IC FOR THERMAL
DISSIPATION.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
SYNC
Synchronization Input. Connect this pin to an external clock between 250 kHz and 1.4 MHz to synchronize the
switching frequency to the external clock. RT can be used to program the phase shift when synchronizing the
external clock.
Frequency Setting. Connect a resistor between the RT and GND pins to program the switching frequency between
250 kHz to 1.4 MHz. When the RT pin is floating, the frequency is set to 620 kHz, and when the RT pin is connected
to VREG, the frequency is set to 1.2 MHz.
RT
TRK
Tracking Input. This pin can be used for tracking and sequencing. If the tracking function is not used, connect TRK
to VREG.
4
5
6
7
8
9
SS
COMP
FB
GND
PGOOD
BST
Soft Start Control. Connect a capacitor from the SS pin to the GND pin to program the soft start time.
Error Amplifier Output. Connect a compensation network from the COMP pin to the GND pin.
Feedback Voltage Sense Input. Connect to a resistor divider from VOUT
.
Analog Ground. Connect to the ground plane.
Power-Good Output (Open-Drain). A pull-up resistor of 100 kΩ is recommended.
Supply Rail for the High-Side MOSFET Gate Drive. Place a 0.1 µF capacitor between the SW pin and the BST pin.
Power Ground. Connect this pin to the ground plane and to the output return side of the output capacitor.
10, 11,
12, 13
PGND
14, 15,
16, 17
SW
Switching Node.
18, 19,
20, 21
PVIN
AVIN
EN
Power Input. Connect this pin to the input power source and connect a bypass capacitor between this pin and
ground.
Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor between
this pin and PVIN.
Precision Enable Input Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
device automatically, connect the EN pin to PVIN. This pin has a 1 MΩ pull-down resistor to GND.
Internal Bias Regulator Output. It supplies the regulated voltage to the internal circuitry. Bypass the VREG pin to
the GND pin with a high quality, low ESR 1 µF ceramic capacitor.
22
23
24
VREG
EPAD
Exposed Pad. Solder the exposed pad to an external ground plane underneath the IC for thermal dissipation.
Rev. B | Page 7 of 23