ADP2118
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC/MODE
FREQ
TRK
1
2
3
4
12 PVIN
11 SW
10 SW
ADP2118
TOP
VIEW
9
SW
FB
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED TO
AN EXTERNAL GROUND PLANE UNDERNEATH
THE IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC/MODE
Synchronization Input (SYNC). Connect this pin to an external clock between 600 kHz and 1.4 MHz to
synchronize the switching frequency to the external clock (see the Oscillator and Synchronization section for
details).
CCM/PFM Selection (MODE). When this pin is connected to VIN, PFM mode is disabled and the ADP2118 only
works in continuous conduction mode (CCM). When this pin is connected to ground, PFM mode is enabled
and becomes active at light loads.
2
3
FREQ
TRK
Frequency Selection. Connect to GND to select 600 kHz and VIN for 1.2 MHz.
Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If the
tracking function is not used, connect TRK to VIN.
4
FB
Feedback Voltage Sense Input. Connect to a resistor divider from VOUT. For the fixed output version, connect
to VOUT directly.
5
GND
PGND
SW
Analog Ground. Connect to the ground plane.
Power Ground. Connect to the ground plane and to the output return side of the output capacitor.
Switch Node Output. Connect to the output inductor.
Power Input Pin. Connect this pin to the input power source. Connect a bypass capacitor between this pin
and PGND.
6, 7, 8
9, 10, 11
12, 13
PVIN
14
15
VIN
EN
Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor
between this pin and PVIN.
Precision Enable Pin. The external resistor divider can be used to set the turn-on threshold. To enable the part
automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND.
16
PGOOD
Power-Good Output (Open Drain). Connect to a resistor to any pull-up voltage <5.5 V.
17 (EPAD)
Exposed Pad
The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation.
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