Datasheet > ADP1882

ADP1882

更新时间： 2022-12-21 23:55:31

品牌	Logo	应用领域
亚德诺 - ADI		控制器
页数	文件大小	规格书
40页	1910K
描述
Synchronous Current-Mode with Constant On-Time,PWM Buck Controller

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ADP1882 数据手册

ADP1882/ADP1883

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

COMP/EN

10 BST

ADP1882/

ADP1883

TOP VIEW

(Not to Scale)

DRVH

PGND

DRVL

GND

VDD

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

VIN

COMP/EN

High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.

Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.

Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.

GND

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground

plane (see the Layout Considerations section).

VDD

Bias Voltage Supply for the ADP1882/ADP1883 Controller, Including the Output Gate Drivers. A bypass capacitor

of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended.

Drive Output for the External Lower-Side N-Channel MOSFET. This pin also serves as the current-sense gain

setting pin (see Figure 69).

DRVL

PGND

DRVH

Power GND. Ground for the lower-side gate driver and lower-side N-channel MOSFET.

Drive Output for the External Upper-Side, N-Channel MOSFET.

Switch Node Connection.

BST

Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be

connected between VDD and BST for increased gate drive capability.

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