Datasheet > ADP1878-1.0-EVALZ

ADP1878-1.0-EVALZ

更新时间： 2022-10-09 10:08:22

品牌	Logo	应用领域
亚德诺 - ADI		控制器
页数	文件大小	规格书
40页	2501K
描述
Synchronous Buck Controller

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ADP1878-1.0-EVALZ 数据手册

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第3页

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第4页

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第5页

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第7页

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第8页

浏览型号ADP1878-1.0-EVALZ的Datasheet PDF文件第9页

ADP1878/ADP1879

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP1878/ADP1879

VIN

COMP

BST

DRVH

PGND

DRVL

PGOOD

GND

RES

VREG

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO THE

ANALOG GROUND PIN (GND).

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

No.

Mnemonic Description

VIN

High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET.

COMP

Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see

the Compensation Network section).

GND

IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC.

Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.

Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout

Considerations section).

RES

VREG

Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).

Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers).

Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are

recommended.

Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value

of 10 nF for every 1 ms of soft start delay.

PGOOD

DRVL

Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown.

Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used.

Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin

(see Figure 69).

PGND

DRVH

Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET.

Drive Output for the External High-Side N-Channel MOSFET.

Switch Node Connection.

Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected

between VREG and BST for increased gate drive capability.

BST

Exposed Pad. Connect the exposed pad to the analog ground pin (GND).

Rev. A | Page 6 of 40

1...3 4 567 8 9...40

下载PDF

与ADP1878-1.0-EVALZ相关器件

型号	品牌	描述	获取价格	数据表
ADP1878ACPZ-0.3-R7	ADI	Synchronous Buck Controller	获取价格
ADP1878ACPZ-0.6-R7	ADI	Synchronous Buck Controller	获取价格
ADP1878ACPZ-1.0-R7	ADI	Synchronous Buck Controller	获取价格
ADP1879	ADI	具有恒定导通时间、谷值电流模式和省电模式的同步降压控制器	获取价格
ADP1879-0.3-EVALZ	ADI	Synchronous Buck Controller	获取价格
ADP1879-0.6-EVALZ	ADI	Synchronous Buck Controller	获取价格