Datasheet > ADP1713AUJZ-0.8-R71

ADP1713AUJZ-0.8-R71

更新时间： 2022-04-25 03:32:37

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
16页	491K
描述
300 mA, Low Dropout CMOS Linear Regulator

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ADP1712/ADP1713/ADP1714

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

OUT

GND

OUT

GND

OUT

BYP

GND

OUT

TRK

ADP1712

ADP1713

ADP1714

ADJUSTABLE

FIXED

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

ADJ

Figure 5. 5-Lead TSOT (UJ-Suffix)

Figure 6. 5-Lead TSOT (UJ-Suffix)

Figure 7. 5-Lead TSOT (UJ-Suffix)

Figure 8. 5-Lead TSOT (UJ-Suffix)

Table 4. Pin Function Descriptions

ADP1712 ADP1712

Fixed

Pin No.

Adjustable ADP1713 ADP1714

Pin No.

Mnemonic Description

GND

Regulator Input Supply. Bypass IN to GND with a 2.2 μF or greater capacitor.

Ground.

Enable Input. Drive EN high to turn on the regulator; drive it low to turn

off the regulator. For automatic startup, connect EN to IN.

Soft Start. Connect a capacitor between SS and GND to set the output

start-up time.

Adjust. A resistor divider from OUT to ADJ sets the output voltage.

Bypass. Connect a 1 nF or greater capacitor (10 nF recommended)

between BYP and GND to reduce the internal reference noise for low

noise applications.

Track. The output follows the voltage placed on the TRK pin. (See the

Theory of Operation section for a more detailed description.)

ADJ

BYP

TRK

OUT

Regulated Output Voltage. Bypass OUT to GND with a 2.2 μF or greater

capacitor.

Rev. A | Page 6 of 16

1...3 4 567 8 9...16

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