ADP1706/ADP1707/ADP1708
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
EN
GND
IN
1
2
3
4
8
7
6
5
SS
PIN 1
EN
GND
IN
1
2
3
4
INDICATOR
8
7
6
5
SS
ADP1706
TOP VIEW
(Not to Scale)
SENSE
OUT
OUT
SENSE
OUT
OUT
ADP1706
TOP VIEW
(Not to Scale)
IN
IN
Figure 4. 8-Lead SOIC, ADP1706
Figure 5. 8-Lead LFCSP, ADP1706
EN
GND
IN
1
2
3
4
8
7
6
5
TRK
PIN 1
EN
GND
IN
1
2
3
4
INDICATOR
8
7
6
5
TRK
ADP1707
TOP VIEW
(Not to Scale)
SENSE
OUT
SENSE
OUT
ADP1707
TOP VIEW
IN
OUT
(Not to Scale)
IN
OUT
Figure 6. 8-Lead SOIC, ADP1707
Figure 7. 8-Lead LFCSP, ADP1707
EN
GND
IN
1
2
3
4
8
7
6
5
ADJ
PIN 1
EN
GND
IN
1
2
3
4
INDICATOR
8
7
6
5
ADJ
ADP1708
TOP VIEW
(Not to Scale)
SENSE
OUT
SENSE
OUT
ADP1708
TOP VIEW
(Not to Scale)
IN
OUT
IN
OUT
Figure 8. 8-Lead SOIC, ADP1708
Figure 9. 8-Lead LFCSP, ADP1708
Table 4. Pin Function Descriptions
ADP1706
Pin No.
ADP1707
Pin No.
ADP1708
Pin No.
Mnemonic Description
1
1
1
EN
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the
regulator. For automatic startup, connect EN to IN.
2
2
2
GND
IN
OUT
SENSE
Ground.
3, 4
5, 6
7
3, 4
5, 6
7
3, 4
5, 6
7
Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor.
Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor.
Sense. Measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect
of IR drop between the regulator output and the load.
8
N/A
N/A
8
N/A
N/A
SS
TRK
Soft Start. A capacitor connected to this pin determines the soft start time.
Track. The output follows the voltage applied at the TRK pin. See the Theory of
Operation section for a more detailed description.
N/A
EP
N/A
EP
8
EP
ADJ
EP
Adjust. A resistor divider from OUT to ADJ sets the output voltage.
The exposed pad on the bottom of the SOIC package and the LFCSP package. EP
enhances thermal performance and is electrically connected to GND inside the
package. User is recommended to connect EP to the ground plane on the board.
Rev. 0 | Page 6 of 20