ADP1147-3.3/ADP1147-5
AP P LICATIO NS
D eter m ining the O utput Cur r ent and the Value for R SENSE
T he value selected for RSENSE is determined by the required
output current. T he current comparator C has a threshold volt-
age range of 10 mV/RSENSE to 150 mV/RSENSE maximum. T his
threshold sets the peak current in the external inductor and
yields a maximum output current of:
T he ADP1147 family of regulators incorporate a current mode,
constant off-time architecture to switch an external P-channel
MOSFET . T he external MOSFET can be switched at frequen-
cies up to 250 kHz. T he switching frequency of the device is
determined by the value selected for capacitor CT .
A regulated output voltage is maintained by the feedback volt-
age at the SENSE(–) pin. T he SENSE(–) pin is connected to an
internal voltage divider. T he voltage from this internal divider is
fed to comparator V, and gain block G. It is then compared to
an internal 1.25 volt reference.
IRIPPLE
p p
−
IMAX = IPEAK
–
2
T he resistance values for RSENSE can range from 20 mΩ to
200 mΩ. A graph for selecting RSENSE vs. the maximum out-
put current is shown in Figure 3.
T he ADP1147 is capable of maintaining high levels of efficiency
by automatically switching between the power saving and con-
tinuous modes. T he internal R-S flip-flop # 2 controls the device
in the power saving mode, and gain block G assumes control
when the device is in the continuous mode of operation.
T he value of RSENSE can be determined by using the following
equation:
RSENSE (in mΩ) = 100/IMAX
T his equation allows for a design margin due to component
variations.
During the P-MOSFET on time, the voltage developed across
RSENSE is monitored by the SENSE(–) and SENSE(+) pins of
the device. When this voltage reaches the threshold level of
comparator C the output trips, switching the P drive to VIN, and
turns the external P-MOSFET off. At this point capacitor CT
begins to discharge at a rate that is determined by the off-time
controller. T he CT discharge current is proportional to the
voltage measured at the SENSE(–) pin. When the voltage on
cap CT decays to the threshold voltage (VT H 1), comparator T
switches and sets R-S flip-flop # 1. T his forces the P-drive out-
put low, and turns on the P-MOSFET . T he sequence is then
repeated. As the load current is increased, the output voltage
starts to drop. T his causes the gain circuit to raise the threshold
of the current comparator, and the load current is now tracked.
T he following equations are used to approximate the trip point
for the power savings mode and the peak short circuit current.
IPOWER SAVINGS ~ 5 mV/RSENSE + VO tOFF/2L
ISC(PK) = 150 mV/RSENSE
T he ADP1147 automatically increases the tOFF time when a
short circuit condition is encountered. T his allows sufficient
time for the inductor to decay between switching cycles. Due to
the resulting inductor ripple current the average short circuit
current ISC(AVG) is reduced to approximately IMAX
.
D eter m ining the O per ating Fr equency and Selecting Values
for CT and L
T he ADP1147 incorporates a constant off-time architecture to
switch an external P-MOSFET . T he off-time (tOFF) is deter-
mined by the value of the external timing cap CT . When the
P-MOSFET is turned on the voltage across CT is charged to
approximately 3.3 volts. During the switch off-time the voltage
on CT is discharged by a current that is proportional to the
voltage level of VOUT . T he voltage across CT is representative of
the current in the inductor, which decays at a rate that is pro-
portional to VOUT . Due to this relationship the value of the
inductor must track the value selected for CT .
When load currents are low, comparator B sets the R-S flip-flop
# 2 and asserts the power savings mode of operation. Compara-
tor B monitors the voltage developed across RSENSE. As the load
current decreases to 50% of the designed inductor ripple cur-
rent, the voltage reverses polarity. T his reversal causes compara-
tor B to trip, setting the Q-bar output of R-S flip-flop # 2 to a
logic zero, and interrupts the cycle by cycle operation of the
output. The output storage capacitors are then slowly discharged
by the load. When the output cap voltage decays to the VOS level
of comparator V, it resets flip-flop # 2, and the normal cycle by
cycle mode of operation resumes. If load currents are extremely
small, the time it takes for flip-flop # 2 to reset increases. During
the extended wait for reset period, capacitor CT will discharge
below the value of VT H2 causing comparator S to trip. T his
forces the internal sleep bar low and the device enters the sleep
mode. A significant amount of the IC is disabled during the
sleep mode, reducing the ground current from 1.6 mA to
160 µA, typical. In sleep mode the P-MOSFET is turned off
until additional inductor current is required. T he sleep mode is
terminated when flip-flop # 2 is reset.
T he following equation is used to determine the desired con-
tinuous mode operating frequency:
VOUT +VD
1−
VIN +VD
CT =
1. 3 × 104 × f
VD = the voltage drop across the Schottky diode.
T he graph in Figure 4 can be used to help determine the capaci-
tance value of CT vs. the operating frequency and input voltage.
T he P-MOSFET gate charge losses increase with the operating
frequency and results in lower efficiency (see the Efficiency
section).
Due to the constant off-time architecture, the input voltage has
an effect on the device switching frequency. T o limit the effects
of this variation in frequency the discharge current is increased
as the device approaches the dropout voltage of VIN +1.5 V. In
the dropout mode the P-MOSFET is constantly turned on.
REV. 0
–7–
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
