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ADN2860

更新时间： 2024-02-05 19:43:33
品牌 Logo 应用领域
亚德诺 - ADI 电位器存储
页数 文件大小 规格书
15页 1125K
描述
3-Channel Digital Potentiometer with Nonvolatile Memory

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ADN2860 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：4 X 4 MM, LFCSP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.91其他特性：IT CAN ALSO OPERATE FROM A 3 TO 5.5V SINGLE SUPPLY
标称带宽：0.125 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：S-XQCC-N24
JESD-609代码：e0长度：4 mm
标称负供电电压：-2.5 V功能数量：1
位置数：512端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：VQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：2.5 V最小电阻器端电压：-2.5 V
座面最大高度：1 mm子类别：Digital Potentiometers
标称供电电压：2.5 V表面贴装：YES
标称温度系数：35 ppm/ °C温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED标称总电阻：250000 Ω
宽度：4 mmBase Number Matches：1

ADN2860 数据手册

 浏览型号ADN2860的Datasheet PDF文件第1页浏览型号ADN2860的Datasheet PDF文件第2页浏览型号ADN2860的Datasheet PDF文件第4页浏览型号ADN2860的Datasheet PDF文件第5页浏览型号ADN2860的Datasheet PDF文件第6页浏览型号ADN2860的Datasheet PDF文件第7页 
Preliminary Technical Data  
ADN2860  
ADN2860 ELECTRICAL CHARACTERISTICS 25k, 250k VERSIONS  
( VDD = 3V to 5.5V and –40C <TA<+85C, unless otherwise noted)  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Units  
DYNAMIC CHARACTERISTICS5, 9  
Bandwidth –3dB  
Total Harmonic Distortion  
VW Settling Time  
BW  
THDW  
tS  
VDD/VSS = +/-2.5 V, RAB = 25 kΩ / 250 kΩ  
VA =1Vrms, VB = 0V, f=1 kHz  
VA= VDD, VB=0V, VW=0.50% error band,  
125/12  
0.05  
kHz  
%
code 000H to 200H. RAB = 25 k/250 kΩ  
RAB = 25 kΩ / 250 kΩ, TA = 25oC  
4 / 36  
20 / 64  
µs  
nV√Hz  
Resistor Noise Spectral Density  
eN_WB  
CT  
Crosstalk (CW1/CW2  
)
VA = VDD, VB = 0V, Measured VW1 with VW2  
making full scale change, RAB = 25 k/250 kΩ  
VDD = VA1 = +2.5 V, VSS = VB1 = -2.5 V, Measure  
VW1 with VW2 = 5V p-p @ f = 1kHz, Code1 = 200H,  
Code 2 = 3FFH, RAB = 25 kΩ / 250 kΩ  
90/21  
nV-s  
dB  
Analog Crosstalk  
CTA  
-81/-62  
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)  
SCL Clock Frequency  
fSCL  
t1  
t2  
t3  
t4  
0
400  
KHz  
µs  
ns  
µs  
µs  
ns  
tBUF Bus free time between STOP & START  
tHD;STA Hold Time (repeated START)  
tLOW Low Period of SCL Clock  
tHIGH High Period of SCL Clock  
1.3  
600  
1.3  
0.6  
600  
After this period the first clock pulse is generated  
50  
tSU;STA Setup Time For START Condition t5  
tHD;DAT Data Hold Time  
tSU;DAT Data Setup Time  
tR Rise Time of both SDA & SCL signals t8  
tF Fall Time of both SDA & SCL signals  
tSU;STO Setup time for STOP Condition  
t6  
t7  
900  
ns  
ns  
ns  
ns  
100  
600  
300  
300  
t9  
t10  
ns  
NOTES:  
1.  
2.  
Typical represent average readings at +25°C, VDD = +5V.  
Resistor position non-linearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the  
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit.  
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.  
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.  
Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
Guaranteed by design and not subject to production test.  
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value  
results in the minimum overall power consumption.  
3.  
4.  
5.  
6.  
7.  
P
is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.  
DISS  
DD DD  
8.  
9.  
All dynamic characteristics use VDD = +5V.  
See timing diagram for location of measured values.  
10. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700,000 cycles.  
11. Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction  
temperature.  
The ADN2860 contains 21,035 transistors. Die size: 88.2 mil x 87.0 mil, 7673 sq. mil.  
Specifications Subject to Change without Notic  
Page 3 of 15  
REV. PrD  
1234567...15

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