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ADN2818ACPZ-RL

更新时间： 2024-01-12 22:50:04

品牌	Logo	应用领域
亚德诺 - ADI		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式时钟
页数	文件大小	规格书
40页	813K
描述
Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

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技术参数
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ADN2818ACPZ-RL 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.25
Is Samacsys：	N	应用程序：	SONET;SDH
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.217 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	5 mm	Base Number Matches：	1

ADN2818ACPZ-RL 数据手册

Data Sheet

ADN2817/ADN2818

REVISION HISTORY

1/13 Rev. D to Rev. E

Changes to Table 19 ........................................................................32

Changes to Table 20 ........................................................................34

Moved Revision History Section.....................................................3

Change to Table 8............................................................................15

Changes to Table 15 ........................................................................17

Changes to Rate Selectivity Section..............................................28

2/09—Rev. A to Rev. B

Updated Outline Dimensions........................................................37

Changes to Ordering Guide...........................................................37

1/12—Rev. C to Rev. D

8/08—Rev. 0 to Rev. A

Changes to Figure 14 ......................................................................12

Updated Outline Dimensions........................................................37

Changes to Features Section, General Description Section, and

Figure 1...............................................................................................1

Added Bit Rate Monitor Specifications Section and Table 4;

Renumbered Sequentially ................................................................7

Changes to Figure 5 and Table 6 ...................................................10

Changes to Table 7 and Table 8 .....................................................14

Changes to Table 14 ........................................................................15

Added Table 15................................................................................15

Added Table 16 ................................................................................16

Added Sample Phase Adjust Section and Bit Error Rate (BER)

Monitor Section...............................................................................23

Added Figure 32; Renumbered Sequentially...............................24

Changes to Figure 36 ......................................................................29

Added Exposed Pad Notation to Outline Dimensions..............37

3/10—Rev. B to Rev. C

Changes to Features Section and Applications Section ...............1

Changes to Thermal Resistance Section ........................................9

Added Table 6; Renumbered Sequentially.....................................9

Changes to Table 7 ..........................................................................10

Changes to Table 8 ..........................................................................14

Changes to Table 14 ........................................................................15

Deleted Table 16; Renumbered Sequentially...............................16

Changes to Table 16 ........................................................................16

Changes to I²C Interface Section...................................................24

Changed f_REFRatio to DIV_FREF Ratio.......................................25

Changes to Initiate Frequency Acquisition, Rate Selectivity,

Double Data Rate Mode, and PRBS Generator/Detector

7/07—Revision 0: Initial Version

Sections.............................................................................................27

Rev. E | Page 3 of 40

1 234 5 6 7...40

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与ADN2818ACPZ-RL相关器件

型号	品牌	描述	获取价格	数据表
ADN2818ACPZ-RL7	ADI	Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs	获取价格
ADN2819	ADI	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp	获取价格
ADN2819ACP-CML	ADI	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp	获取价格
ADN2819ACP-CML-RL	ADI	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp	获取价格
ADN2819ACPZ-CML1	ADI	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp	获取价格
ADN2819ACPZ-CML-RL	ADI	Multi Rate Limiting Amplifier and Clock and Data Recovery ICs	获取价格

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