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ADMC401-PB PDF预览

ADMC401-PB

更新时间: 2024-02-15 19:16:06
品牌 Logo 应用领域
亚德诺 - ADI 电机控制器
页数 文件大小 规格书
60页 413K
描述
Single-Chip, DSP-Based High Performance Motor Controller

ADMC401-PB 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:QFP, QFP144,.87SQ,20
针数:144Reach Compliance Code:compliant
风险等级:8.4JESD-30 代码:S-PQFP-G144
JESD-609代码:e3湿度敏感等级:3
端子数量:144最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:5 V认证状态:Not Qualified
子类别:Motion Control Electronics标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

ADMC401-PB 数据手册

 浏览型号ADMC401-PB的Datasheet PDF文件第2页浏览型号ADMC401-PB的Datasheet PDF文件第3页浏览型号ADMC401-PB的Datasheet PDF文件第4页浏览型号ADMC401-PB的Datasheet PDF文件第6页浏览型号ADMC401-PB的Datasheet PDF文件第7页浏览型号ADMC401-PB的Datasheet PDF文件第8页 
ADMC401  
Parameter  
Min  
Max  
Unit  
Clock Signals  
tCK is defined as 0.5tCKI. The ADMC401 uses an input clock  
with a frequency equal to half the instruction rate; a 13 MHz  
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor  
cycle (equivalent to 26 MHz). tCK values within the range of  
0.5tCKI period should be substituted for all relevant timing  
parameters to obtain specification value.  
Example: tCKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.  
Timing Requirements:  
tCKI  
tCKIL  
tCKIH  
CLKIN Period  
CLKIN Width Low  
CLKIN Width High  
76.9  
20  
20  
150  
20  
ns  
ns  
ns  
Switching Characteristics:  
tCKL  
tCKH  
tCKOH  
CLKOUT Width Low  
CLKOUT Width High  
CLKIN High to CLKOUT High  
0.5tCK – 10  
0.5tCK – 10  
0
ns  
ns  
ns  
Control Signals  
Timing Requirement:  
1
tRSP  
RESET Width Low  
5tCK  
ns  
PWM Shutdown Signals  
Timing Requirements:  
tPWMTPW  
tPIOPWM  
PWMTRIP Width Low  
PIO Width Low  
tCK  
2tCK  
ns  
ns  
ADC Signals  
Timing Requirements:  
tCSI  
tCSE  
Internal Convert Start Width High  
External Convert Start Width High  
2tCK  
2tCK  
ns  
ns  
NOTE  
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal  
oscillator start-up time).  
tCKI  
tCKIH  
CLKIN  
tCKOH  
tCKH  
tCKIL  
CLKOUT  
tCKL  
Figure 1. Clock Signals  
–5–  
REV. B  

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