ADM9240ARUZ

更新时间： 2024-02-02 22:01:56

品牌	Logo	应用领域
亚德诺 - ADI		微处理器监控
页数	文件大小	规格书
22页	283K
描述
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24, TSSOP-24, Power Management Circuit

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技术参数
数据手册

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ADM9240ARUZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	TSSOP
包装说明：	TSSOP-24	针数：	24
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.15
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e3
长度：	7.8 mm	信道数量：	1
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.1 mm	最大供电电压 (Vsup)：	5.75 V
最小供电电压 (Vsup)：	2.85 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4.4 mm
Base Number Matches：	1

ADM9240ARUZ 数据手册

ADM9240

P IN FUNCTIO N D ESCRIP TIO NS

D escription

P in Num ber Mnem onic

NT EST _OUT /A0

Digital I/O. Dual Function Pin. The lowest order programmable bit of the Serial Bus Address.

T his pin functions as an output when doing a NAND T ree test.

Digital Input. T he highest order programmable bit of the Serial Bus Address.

Digital I/O. Serial Bus Bidirectional Data. Open-drain output.

Digital Input. Serial Bus Clock.

SDA

SCL

FAN1

FAN2

Digital Input. 0 to V_CCamplitude fan tachometer input.

Digital I/O. An active high input from an external circuit that latches a Chassis Intrusion

event. T his line can go high without any clamping action regardless of the powered state of

the ADM9240. T he ADM9240 provides an internal open drain on this line, controlled by

Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line,

to reset the external Chassis Intrusion Latch.

GNDD

V_CC

Digital Ground. Internally connected to all of the digital circuitry.

Power (+2.85 V to +5.75 V). T ypically powered from +3.3 V or +5 V power rail. Bypass with

the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass

capacitors.

INT

Digital Output. Interrupt Request (open drain). T he output is enabled when Bit 1 of the

Configuration Register is set to 1. T he default state is disabled.

NT EST _IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND T ree mode board-

level connectivity testing. Refer to section on NAND T ree testing. Also functions as a pro-

grammable analog output when NAND T ree is not selected

RESET

Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 20 ms minimum

pulsewidth. Available when enabled via Bit 7 in Register 44h, and set using Bit 4 in Register

40h. Also acts as reset input when pulled low (e.g., power-on reset).

GNDA

+V_CCP2

Analog Ground. Internally connected to all analog circuitry. T he ground reference for all

analog inputs.

Analog Input. Monitors processor core voltage +V_CCP2(0 V–3.6 V). Can also be used to

monitor the –12 V supply by adding two external resistors.

+12 V_IN

+5 V_IN

Analog Input. Monitors +12 V supply.

Analog Input. Monitors +5 V supply.

+3.3 V_IN

+2.5 V_IN

+V_CCP1

VID4

Analog Input. Monitors +3.3 V supply.

Analog Input. Monitors +2.5 V supply.

Analog Input. Monitors processor core voltage +V_CCP1(0 V–3.6 V).