ADM202JRN

更新时间： 2024-02-28 06:33:08

品牌	Logo	应用领域
亚德诺 - ADI		驱动器
页数	文件大小	规格书
6页	308K
描述
High Speed, +5 V, 0.1 uF CMOS RS-232 Driver/Receivers

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技术参数
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ADM202JRN 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.74
其他特性：	EXTERNAL CHARGE PUMP	差分输出：	NO
驱动器位数：	2	高电平输入电流最大值：	0.000025 A
输入特性：	SCHMITT TRIGGER	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	EIA-232-E; V.28	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	10.3 mm
湿度敏感等级：	1	功能数量：	2
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		最小输出摆幅：	10 V
最大输出低电流：	0.0016 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	最大接收延迟：	5000 ns
接收器位数：	2	座面最大高度：	2.72 mm
子类别：	Line Driver or Receivers	最大压摆率：	4 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	BICMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	最大传输延迟：	5000 ns
宽度：	7.5 mm	Base Number Matches：	1

ADM202JRN 数据手册

ADM202/ADM203

R_IN

Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is

connected on each of these inputs.

R_OUT

Receiver Outputs. These are TTL/CMOS levels.

GENERAL INFORMATION

The ADM202/ADM203 is an RS-232 drivers/receivers designed

to solve interface problems by meeting the EIA-232E specifica-

tions while using a single digital +5 V supply. The EIA standard

requires transmitters that will deliver ±5 V minimum on the

transmission channel and receivers that can accept signal levels

down to ±3 V. The parts achieve this by integrating step up

voltage converters and level shifting transmitters and receivers

onto the same chip. CMOS technology is used to keep the

power dissipation to an absolute minimum.

V+

GND

FROM

VOLTAGE

DOUBLER

GND

V– = – (V+)

INTERNAL

OSCILLATOR

Figure 3. Charge Pump Voltage Inverter

Transmitter (Driver) Section

The drivers convert TTL/CMOS input levels into EIA-232-E

output levels. With V_CC= +5 V and driving a typical EIA-232-E

load, the output voltage swing is ±9 V. Even under worst case

conditions the drivers are guaranteed to meet the ±5 V

EIA-232-E minimum requirement.

The ADM203 uses internal capacitors and, therefore, no exter-

nal capacitors are required.

The ADM202 contains an internal voltage doubler and a voltage

inverter which generates ±10 V from the +5 V input. External

0.1 µF capacitors are required for the internal voltage converter.

The ADM202/ADM203 is a modification, enhancement and

improvement to the AD230–AD241 family and derivatives

thereof. It is essentially plug-in compatible and does not have

materially different applications.

The input threshold levels are both TTL and CMOS compat-

ible with the switching threshold set at V_CC/4. With a nominal

_CC= 5 V the switching threshold is 1.25 V typical. Unused

inputs may be left unconnected, as an internal 400 kΩ pull-up

resistor pulls them high forcing the outputs into a low state.

CIRCUIT DESCRIPTION

The internal circuitry consists of three main sections. These are

As required by the EIA-232-E standard the slew rate is limited

to less than 30 V/µs without the need for an external slew limiting

capacitor and the output impedance in the power-off state is

greater than 300 Ω.

(a) A Charge Pump Voltage Converter

(b) RS-232 to TTL/CMOS Receivers

Receiver Section

The receivers are inverting level shifters that accept EIA-232-E

input levels (±5 V to ±15 V) and translate them into 5 V TTL/

CMOS levels. The inputs have internal 5 kΩ pull-down resistors

to ground and are also protected against overvoltages of up to

±30 V. The guaranteed switching thresholds are 0.8 V minimum

and 2.4 V maximum which are well within the ±3 V EIA-232

requirement. The low level threshold is deliberately positive as it

ensures that an unconnected input will be interpreted as a low

level.

Charge Pump DC-DC Voltage Converter

The charge pump voltage converter consists of an oscillator and

a switching matrix. The converter generates a ±10 V supply

from the input 5 V level. This is done in two stages using a

switched capacitor technique as illustrated below. First, the 5 V

input supply is doubled to 10 V using capacitor C1 as the

charge storage element. The 10 V level is then inverted to gen-

erate –10 V using C2 as the storage element.

Capacitors C3 and C4 are used to reduce the output ripple.

Their values are not critical and can be reduced if higher levels

of ripple are acceptable. The charge pump capacitors C1 and

C2 may also be reduced at the expense of higher output imped-

ance on the V+ and V– supplies. On the ADM203, all capaci-

tors C1 to C4 are molded into the package.

The receivers have Schmitt trigger input with a hysteresis level

of 0.5 V. This ensures error free reception both for noisy inputs

and for inputs with slow transition times.

The V+ and V– supplies may also be used to power external

circuitry if the current requirements are small.

V+ = 2V

GND

INTERNAL

OSCILLATOR

Figure 2. Charge Pump Voltage Doubler

–4–

REV. 0

1 2 345 6

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