Datasheet > ADM1175-3ARMZ-R7

ADM1175-3ARMZ-R7

更新时间： 2024-02-27 20:07:07

品牌	Logo	应用领域
亚德诺 - ADI		监控控制器
页数	文件大小	规格书
24页	587K
描述
Hot Swap Controller and Digital Power Monitor with Convert Pin

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ADM1175-3ARMZ-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP10,.19,20	针数：	10
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.64
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-PDSO-G10	JESD-609代码：	e3
长度：	3 mm	湿度敏感等级：	1
信道数量：	1	功能数量：	1
端子数量：	10	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.15/14 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	Power Management Circuits	最大供电电流 (Isup)：	3 mA
最大供电电压 (Vsup)：	16.5 V	最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm	Base Number Matches：	1

ADM1175-3ARMZ-R7 数据手册

ADM1175

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC

SENSE

ON/ONB

GND

10 GATE

CONV

ADR

SDA

SCL

ADM1175

TOP VIEW

(Not to Scale)

TIMER

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

VCC

Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage

lockout (UVLO) circuit resets the ADM1175 when a low supply voltage is detected.

SENSE

Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current

limit. The hot swap operation of the ADM1175 controls the external FET gate to maintain the (V_VCC− V_SENSE

voltage at 100 mV or below.

)

ON/ONB

Undervoltage or Overvoltage Input Pin. This pin is active high on the ADM1175-1 and ADM1175-2 and

active-low on the ADM1175-3 and ADM1175-4. An internal ON comparator has a trip threshold of 1.3 V,

and the output of this comparator is used as an enable for the hot swap operation. For the ON pin variants

with an external resistor divider from VCC to GND, this pin can be used to enable the hot swap operation

on a specific voltage on VCC, giving an undervoltage function. Similarly, for the ONB pin variants, an external

resistor divider can be used to create an overvoltage function, where the divider sets a voltage on VCC at

which the hot swap operation is switched off, pulling the GATE to ground.

GND

TIMER

Chip Ground Pin.

Timer Pin. An external capacitor, C_TIMER, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.

The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection

with an external Zener can be used to force this pin high.

SCL

SDA

ADR

I²C Clock Pin. Open-drain input requires an external resistive pull-up.

I²C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.

I²C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four

different I²C addresses.

CONV

GATE

Convert Start Pin. A high level on this pin enables an ADC conversion. The state of an internal control register,

which is set through the I²C interface, configures the part to convert current only, voltage only, or both

channels when the convert pin is asserted.

GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the

FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET

GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)

by modulating the GATE pin.

Rev. 0 | Page 7 of 24

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