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ADM1051JR-REEL

更新时间： 2024-01-05 11:28:05

品牌	Logo	应用领域
亚德诺 - ADI		控制器
页数	文件大小	规格书
10页	177K
描述
IC DUAL SWITCHING CONTROLLER, PDSO8, SOIC-8, Switching Regulator or Controller

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ADM1051JR-REEL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP,
针数：	8	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
模拟集成电路 - 其他类型：	DUAL SWITCHING CONTROLLER	最大输入电压：	12.72 V
最小输入电压：	11.28 V	标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	功能数量：	1
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.59 mm
表面贴装：	YES	切换器配置：	SINGLE
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	Base Number Matches：	1

ADM1051JR-REEL 数据手册

ADM1051/ADM1051A

HICCUP MODE FAULT PROTECTION

APPLICATIONS INFORMATION

Hiccup Mode Fault Protection is a simple method of protecting

the external power device without the added cost of external sense

resistors or a current sense pin on the ADM1051/ADM1051A. In

the event of a short-circuit condition at the output, the output

voltage will fall. When the output voltage of a channel falls

20% below the nominal voltage, this is sensed by the hiccup com-

parator and the channel will go into Hiccup Mode, where the

enable signal to the control amplifier is pulsed on and off

with a 1:40 duty cycle. As mentioned earlier, Hiccup Mode

does not operate on Channel 2 of the ADM1051A.

PCB LAYOUT

For optimum voltage regulation, the loads should be placed as

close as possible to the source of the output MOSFETs and

feedback to the sense inputs should be taken from a point as

close to the loads as possible. The PCB tracks from the loads

back to the sense inputs should be separate from the output

tracks and not carry any load current.

Similarly, the ground connection to the ADM1051/ADM1051A

should be made as close as possible to the ground of the loads, and

the ground track from the loads to the ADM1051/ADM1051A

should not carry load current. Good and bad layout practice is

illustrated in Figure 5.

To prevent the device inadvertently going into Hiccup Mode dur-

ing power-up or during channel enabling, the Hiccup Mode is

held off for approximately 60 ms on both channels. By this time

the output voltage should have reached its correct value. In the

case of power-up, the hold-off period starts when V_CCreaches

the power-on reset threshold of 6 V–9 V. In the case of channel

enabling, the hold-off period starts when SHDN is taken high.

Note that the hold-off timeout applies to both channels even if

only one channel is disabled/enabled.

GOOD

12V

FORCE 1

SENSE 1

FORCE 2

3.3V

As the 3.3 V input to the drain of the MOSFET is not monitored,

it should ideally rise at the same or a faster rate than V_CC. At the

very least it must be available in time for V_OUTto reach its final

value before the end of the power-on delay. If the output voltage

is still less than 80% of the correct value after the power-on delay,

the device will go into Hiccup Mode until the output voltage

exceeds 80% of the correct value during a Hiccup Mode on-

period. Of course, if there is a fault condition at the output

during power-up, the device will go into Hiccup Mode after the

power-up delay and remain there until the fault condition is

removed.

SENSE 2

GND

OUT1

OUT2

LOAD 2

LOAD 1

BAD

12V

FORCE 1

SENSE 1

FORCE 2

SENSE 2

OUT1

3.3V

The effect of power-on delay is illustrated in Figure 4. This shows

an ADM1051/ADM1051A being powered up with a fault

condition. The output current rises to a very high value dur-

ing the power-on delay, then the device goes into Hiccup Mode

and the output is pulsed on and off at 1:40 duty cycle. When the

fault condition is removed, the output voltage recovers to its

normal value at the end of the Hiccup Mode off period.

OUT2

VOLTAGE DROP

BETWEEN OUTPUT

AND LOAD

GND

LOAD 1

LOAD 2

؉ I

VOLTAGE DROP

IN GROUND LEAD

The load current at which the ADM1051/ADM1051A will go

into Hiccup Mode is determined by three factors:

Figure 5. Good and Bad Layout Practice

• the input voltage to the drain of the MOSFET, V_IN

• the output voltage V_OUT(–20%)

• the on-resistance of the MOSFET, R_ON

_HICCUP= (V_IN– (0.8 × V_OUT))/R_ON

It should be emphasized that the Hiccup Mode is not intended

as a precise current limit but as a simple method of protecting

the external MOSFET against catastrophic fault conditions such

as output short-circuits.

–8–

REV. 0

1...5 6 789 10

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