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ADG3241BKS-REEL

更新时间： 2024-01-23 16:48:49
品牌 Logo 应用领域
亚德诺 - ADI 转换器电平转换器开关
页数 文件大小 规格书
12页 210K
描述
2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66

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ADG3241BKS-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：VSSOP, TSSOP6,.08针数：6
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.31
系列：3241JESD-30 代码：R-PDSO-G6
JESD-609代码：e4长度：2 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：1功能数量：1
端口数量：2端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装等效代码：TSSOP6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/3.3 V传播延迟（tpd）：0.225 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：1.25 mmBase Number Matches：1

ADG3241BKS-REEL 数据手册

 浏览型号ADG3241BKS-REEL的Datasheet PDF文件第1页浏览型号ADG3241BKS-REEL的Datasheet PDF文件第2页浏览型号ADG3241BKS-REEL的Datasheet PDF文件第3页浏览型号ADG3241BKS-REEL的Datasheet PDF文件第5页浏览型号ADG3241BKS-REEL的Datasheet PDF文件第6页浏览型号ADG3241BKS-REEL的Datasheet PDF文件第7页 
ADG3241  
PIN CONFIGURATION  
6-Lead SC70  
Table II. Pin Function Descriptions  
SOT-66 Mnemonic Description  
Pin No.  
SC70  
1
2
3
6
5
4
SEL  
BE  
GND  
A
ADG3241  
TOP VIEW  
(Not to Scale)  
1
2
3
4
5
6
6
4
3
5
1
2
BE  
GND  
A
B
VCC  
SEL  
Bus Enable (Active Low)  
Ground Reference  
Port A, Input or Output  
Port B, Input or Output  
Positive Power Supply Voltage  
Level Translation Select  
V
CC  
B
6-Lead SOT-66  
1
2
3
6
5
4
V
BE  
B
CC  
ADG3241  
TOP VIEW  
(Not to Scale)  
SEL  
A
GND  
ORDERING GUIDE  
Package  
Temperature  
Range  
Model  
Description  
Package  
Branding  
ADG3241BKS-REEL  
ADG3241BKS-REEL7  
ADG3241BKS-500RL7  
ADG3241BRY-REEL7  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
Thin Shrink Small Outline Transistor Package (SC70)  
Thin Shrink Small Outline Transistor Package (SC70)  
Thin Shrink Small Outline Transistor Package (SC70)  
Small Outline Transistor Package (SOT-66)  
KS-6  
KS-6  
KS-6  
RY-6-1  
SKA  
SKA  
SKA  
00  
TERMINOLOGY  
VCC  
GND  
VINH  
VINL  
II  
Positive Power Supply Voltage.  
Ground (0 V) Reference.  
Minimum Input Voltage for Logic 1.  
Maximum Input Voltage for Logic 0.  
Input Leakage Current at the Control Inputs.  
IOZ  
IOL  
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.  
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.  
VP  
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when  
the switch input voltage is equal to the supply voltage.  
RON  
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified  
amount of current through the switch.  
CX OFF  
CX ON  
CIN  
OFF Switch Capacitance.  
ON Switch Capacitance.  
Control Input Capacitance. This consists of BE and SEL.  
ICC  
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.  
It is measured when all control inputs are at a logic high or low level and the switches are OFF.  
⌬ICC  
Extra power supply current component for the BE control input when the input is not driven at the supplies.  
t
t
t
PLH, tPHL  
PZH, tPZL  
PHZ, tPLZ  
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant  
RON × CL, where CL is the load capacitance.  
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on  
in response to the control signal, BE.  
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control  
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,  
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)  
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.  
Channel Jitter  
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.  
–4–  
REV. A  
1234567...12

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