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ADG3123BRUZ-REEL

更新时间: 2024-09-30 04:04:31
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描述
8-Channel CMOS Logic to High Voltage Level Translator

ADG3123BRUZ-REEL 数据手册

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8-Channel CMOS Logic to High Voltage  
Level Translator  
ADG3123  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
V
2.3 V to 5.5 V input voltage range  
DDA  
Output voltage levels (VDDA and VDDB to VSS ≤ 35 V)  
Low output voltage levels: down to −24.4 V  
High output voltage levels: up to +35 V  
Rise/fall time: 12 ns/19.5 ns typical  
Propagation delay: 80 ns typical  
Operating frequency: 100 kHz typical  
Ultralow quiescent current: 65 μA typical  
20-lead, Pb-free, TSSOP package  
A1  
ADG3123  
A2  
6
A3  
A4  
A5  
A6  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
CHANNELS  
GND  
V
SS  
APPLICATIONS  
Low voltage to high voltage translation  
TFT-LCD panels  
A7  
A8  
Y7  
Y8  
2
CHANNELS  
Piezoelectric motor drivers  
V
DDB  
Figure 1.  
GENERAL DESCRIPTION  
The ADG3123 is an 8-channel, noninverting CMOS to high  
voltage level translator. Fabricated on an enhanced LC2MOS  
process, the device is capable of operating at high supply  
voltages while maintaining ultralow power consumption.  
The ADG3123 is guaranteed to operate over the −40°C to  
+85°C temperature range and is available in a compact, 20-lead  
TSSOP, Pb-free package.  
The internal architecture of the device ensures compatibility  
with logic circuits running from supply voltages within the 2.3 V to  
5.5 V range. The voltages applied to Pin VDDA, Pin VDDB, and  
Pin VSS set the logic levels available at the outputs on the Y side  
of the device. Pin VDDA and Pin VDDB set the high output level  
for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The  
PRODUCT HIGHLIGHTS  
1. Compatible with a wide range of CMOS logic levels.  
2. High output voltage levels.  
3. Fast rise and fall times coupled with low propagation delay.  
4. Ultralow power consumption.  
VSS pin sets the low output level for all channels. The ADG3123  
can provide output voltages levels down to −10 V for a low  
input level and up to +30 V for a high input logic level. For  
proper operation, VDDB must always be greater than or equal to  
5. Compact, 20-lead TSSOP, Pb-free package.  
VDDA and the voltage between the Pin VDDB and Pin VSS should  
not exceed 35 V.  
The low output impedance of the channels guarantees fast rise  
and fall times even for significant capacitive loads. This feature,  
combined with low propagation delay and low power consump-  
tion, makes the ADG3123 an ideal driver for TFT-LCD panel  
applications.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 

ADG3123BRUZ-REEL 替代型号

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ADG3123BRUZ ADI

完全替代

8-Channel CMOS Logic to High Voltage Level Translator

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