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ADF7012 PDF预览

ADF7012

更新时间: 2024-01-05 11:29:37
品牌 Logo 应用领域
亚德诺 - ADI ISM频段
页数 文件大小 规格书
28页 893K
描述
Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter

ADF7012 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:unknown风险等级:5.07
Is Samacsys:NJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:7.8 mm
湿度敏感等级:1功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.2 mm
标称供电电压:3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

ADF7012 数据手册

 浏览型号ADF7012的Datasheet PDF文件第20页浏览型号ADF7012的Datasheet PDF文件第21页浏览型号ADF7012的Datasheet PDF文件第22页浏览型号ADF7012的Datasheet PDF文件第24页浏览型号ADF7012的Datasheet PDF文件第25页浏览型号ADF7012的Datasheet PDF文件第26页 
ADF7012  
915 MHZ OPERATION  
Deviation  
The recommendations here are guidelines only. The design  
should be subject to internal testing prior to FCC site testing.  
Matching components need to be adjusted for board layout.  
The deviation is set to 19.2 kHz so as to accommodate a  
simple receiver architecture, and also to ensure the available  
spectrum is used efficiently.  
FCC 15.247 and FCC 15.249 are the main regulations governing  
operation in the 902 MHz to 928 MHz Band. FCC 15.247  
requires some form of spectral spreading. Typically, the  
ADF7012 would be used in conjunction with the frequency  
hopping spread spectrum (FHSS) or it may be used in  
conjunction with the digital modulation standard which  
requires large deviation frequencies. Output power of < 1 W  
is tolerated on certain spreading conditions.  
The modulation steps available are in 10 MHz/214 :  
Modulation steps = 610 Hz  
Modulation number = 19.2 kHz/610 Hz = 31.  
Bias Current  
Because low current is desired, a 3 mA VCO bias can be used  
and still ensure oscillation at 928 MHz. Additional bias current  
reduces any spurious noise, but increases current consumption.  
A 3 mA bias current gives the best spurious vs. phase noise  
trade-off.  
Compliance with FCC 15.249 limits the output power to  
−1.5 dBm, but does not require spreading. There are many  
different applications in this band, including remote controls  
for security, sensor interrogation, metering, and home control.  
The PA bias should be set to 5.5 mA to achieve 10 dBm power.  
Loop Filter Bandwidth  
Design Criteria  
915.2MHz center frequency  
FSK modulation  
10 dBm output power  
200 m range  
The loop filter is designed with ADIsimPLL Version 2.5. A  
data rate of 170 kHz is chosen, which allows for data rates of  
> 38.4 kbps. It also attenuates the beat note spurs quickly to  
ensure they have no effect on system performance.  
Meets FCC 15.247  
38.4 kbps data rate  
Design of Harmonic Filter  
The main requirement of the harmonic filter should ensure  
that the third harmonic level is < −41.5 dBm. A fifth-order  
Chebyshev filter is recommended to achieve this, and a  
suggested starting point is given next. The Pi format is chosen  
to minimize the number of inductors in the system.  
The center frequency is 915.2 MHz. It is possible to operate  
the VCO at this frequency. Figure 36 shows the inductor value  
vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft  
inductors such as 0603-CS-1N6XJBU are recommended.  
Additional hopping frequencies can easily be generated by  
changing the N value.  
Component Values—Crystal: 10 MHz  
Loop Filter  
Crystal and PFD  
Icp  
LBW  
C1  
1.44 mA  
170 kHz  
470 pF  
12 nF  
The phase noise requirement is such to ensure that the 20 dB  
bandwidth requirements are met. These are dependant on the  
channel spacing chosen. A typical channel spacing would be  
400 kHz, which would allow 50 channels in 20 MHz and enable  
the design to avoid the edges of the band.  
C2  
C3  
R1  
120 pF  
470 V  
R2  
1.8 kV  
The PFD is chosen so as to minimize spurious levels. There are  
beat note spurious levels at 910 MHz and 920 MHz, but the  
level is usually significantly less than the modulation power.  
They are also attenuated quickly by the loop filter to ensure a  
quick crystal power-up time.  
Matching  
L1  
L2  
C14  
C15  
27 nH  
6.2 nH  
470 pF  
Open  
PFD = 10 MHz − Power-Up Time 1.8 ms (approximately).  
Figure 10 shows a typical power-on time for a 4 MHz crystal.  
Harmonic Filter  
L4  
L5  
CF1  
CF2  
CF3  
8.2 nH  
8.2 nH  
4.7 pF  
6.8 pF  
4.7 pF  
N-Divider  
The N divider is determined as being:  
Nint = 91  
Nfrac = (2130)/4096  
VCO divide-by-2 is not enabled  
Rev. 0 | Page 23 of 28  
 

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