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ADF4360-7BCPRL PDF预览

ADF4360-7BCPRL

更新时间: 2024-01-18 20:50:55
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 929K
描述
IC TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC24, 4 X 4 MM, MO-220-VGGD-2, LFCSP-24, Cellular Telephone Circuit

ADF4360-7BCPRL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC24,.16SQ,20针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.33
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm湿度敏感等级:3
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS电信集成电路类型:BASEBAND CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

ADF4360-7BCPRL 数据手册

 浏览型号ADF4360-7BCPRL的Datasheet PDF文件第2页浏览型号ADF4360-7BCPRL的Datasheet PDF文件第3页浏览型号ADF4360-7BCPRL的Datasheet PDF文件第4页浏览型号ADF4360-7BCPRL的Datasheet PDF文件第5页浏览型号ADF4360-7BCPRL的Datasheet PDF文件第6页浏览型号ADF4360-7BCPRL的Datasheet PDF文件第7页 
50 MHz to 1000 MHz  
Quadrature Demodulator  
AD8348  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
VREF  
IMXO  
IOFS  
IAIN  
IOPP IOPN  
Integrated I/Q demodulator with IF VGA amplifier  
Operating IF frequency 50 MHz to 1000 MHz  
(3 dB IF BW of 500 MHz driven from RS = 200 Ω)  
Demodulation bandwidth 75 MHz  
Linear-in-decibel AGC range 44 dB  
Third-order intercept  
14  
8
13  
6
4
3
BIAS  
CELL  
VREF  
ENBL 15  
5
1
VCMO  
LOIP  
VCMO  
DIVIDE  
BY 2  
IFIP 11  
IFIN 10  
PHASE  
SPLITTER  
28  
LOIN  
IIP3 +28 dBm @ minimum gain (FIF = 380 MHz)  
IIP3 −8 dBm @ maximum gain (FIF = 380 MHz)  
Quadrature demodulation accuracy  
Phase accuracy 0.5°  
Amplitude balance 0.25 dB  
Noise figure 11 dB @ maximum gain (FIF = 380 MHz)  
LO input −10 dBm  
AD8348  
GAIN  
CONTROL  
VGIN 17  
VCMO  
25  
26  
23  
18  
19  
24  
21  
16  
MXIP MXIN ENVG  
QXMO  
QOFS  
QAIN  
QOPP QOPN  
Figure 1.  
Single supply 2.7 V to 5.5 V  
Power-down mode  
Compact, 28-lead TSSOP package  
APPLICATIONS  
QAM/QPSK demodulator  
W-CDMA/CDMA/GSM/NADC  
Wireless local loop  
LMDS  
GENERAL DESCRIPTION  
The AD8348 is a broadband quadrature demodulator with an  
integrated intermediate frequency (IF), variable gain amplifier  
(VGA), and integrated baseband amplifiers. It is suitable for use in  
communications receivers, performing quadrature demodulation  
from IF directly to baseband frequencies. The baseband amplifiers  
are designed to interface directly with dual-channel ADCs, such  
as the AD9201, AD9283, and AD9218, for digitizing and post-  
processing.  
Separate I- and Q-channel baseband amplifiers follow the baseband  
outputs of the mixers. The voltage applied to the VCMO pin sets  
the dc common-mode voltage level at the baseband outputs.  
Typically, VCMO is connected to the internal VREF voltage, but  
it can also be connected to an external voltage. This flexibility  
allows the user to maximize the input dynamic range to the ADC.  
Connecting a bypass capacitor at each offset compensation input  
(IOFS and QOFS) nulls dc offsets produced in the mixer. Offset  
compensation can be overridden by applying an external voltage  
at the offset compensation inputs.  
The IF input signal is fed into two Gilbert cell mixers through  
an X-AMP® VGA. The IF VGA provides 44 dB of gain control.  
A precision gain control circuit sets a linear-in-decibel gain char-  
acteristic for the VGA and provides temperature compensation.  
The LO quadrature phase splitter employs a divide-by-2 frequency  
divider to achieve high quadrature accuracy and amplitude balance  
over the entire operating frequency range.  
The mixers’ outputs are brought off-chip for optional filtering  
before final amplification. Inserting a channel selection filter  
before each baseband amplifier increases the baseband amplifiers’  
signal handling range by reducing the amplitude of high level,  
out-of-channel interferers before the baseband signal is fed into  
the I/Q baseband amplifiers. The single-ended mixer output is  
amplified and converted to a differential signal for driving ADCs.  
Optionally, the IF VGA can be disabled and bypassed. In this  
mode, the IF signal is applied directly to the quadrature mixer  
inputs via the MXIP and MXIN pins.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 

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