Microwave Wideband Synthesizer
with Integrated VCO
Data Sheet
ADF4372
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 62.5 MHz to 16,000 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 39-bit fractional modulus
Typical spurious fPFD: −90 dBc
Integrated rms jitter: 38 fs (1 kHz to 100 MHz)
Normalized phase noise floor: −234 dBc/Hz
The ADF4372 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. The
wideband microwave voltage controlled oscillator (VCO) design
allows frequencies from 62.5 MHz to 16 GHz to be generated.
The ADF4372 has an integrated VCO with a fundamental output
frequency ranging from 4000 MHz to 8000 MHz. In addition, the
VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64
circuit that allows the user to generate radio frequency (RF)
output frequencies as low as 62.5 MHz at RF8x. A frequency
multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x
duplicates the frequency range of RF8x or permits direct access to
the VCO output. To suppress the unwanted products of frequency
multiplication, a harmonic filter exists between the multiplier and
the output stage of RF16x.
f
PFD operation to 250 MHz
Reference input frequency operation to 600 MHz
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x
8,000 MHz to 16,000 MHz output at RF16x
Lock time approximately 3 ms with automatic calibration
Lock time <30 μs with autocalibration bypassed, typical
Analog and digital power supplies: 3.3 V typical
VCO supply voltage: 3.3 V and 5 V
RF output mute function
Control of all on-chip registers is through a 3-wire interface.
The ADF4372 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, and 5 V for the VCO power
supply. The ADF4372 also contains hardware and software
power-down modes.
7mm × 7mm, 48-terminal LGA package
APPLICATIONS
Wireless infrastructure (multicarrier global system for
mobile communication (MC-GSM), 5G)
Test equipment and instrumentation
Clock generation
Aerospace and defense
FUNCTIONAL BLOCK DIAGRAM
VCC_CAL VCC_VCO VCC_LDO VCC_X1 VCC_X2
VCC_MUX VCC_3V VDD_NDIV VDD_LS VCC_LDO_3V VCC_REF VDD_PFD VDD_VP
MUX
MUXOUT
5-BIT R
COUNTER
÷2
DIVIDER
REFP
×2
DOUBLER
RS_SW
REFN
LOCK
DETECT
VCC_REG_OUT
ADF4372
SCLK
SDIO
CS
CHARGE
PUMP
CPOUT
VTUNE
DATA REGISTER
FUNCTION
LATCH
PHASE
COMPARATOR
TRACKING
FILTER
8GHz
TO 16GHz
VCO
RF16P
RF16N
OUTPUT
STAGE
LOW
NOISE
LDO
×2
CORE
INTEGER
FRACTION
MODULUS
REGISTER
62.5MHz TO 8000MHz
REGISTER REGISTER
RF8P
RF8N
1, 2, 4, 8,
16, 32, 64
OUTPUT
STAGE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MUX
62.5MHz TO 8000MHz
N COUNTER
RFAUX8P
RFAUX8N
OUTPUT
STAGE
MUX
GND
Figure 1.
Rev. 0
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