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ADF4213BCP-REEL7

更新时间： 2024-01-13 23:41:05
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 248K
描述
IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC20, CSP-20, PLL or Frequency Synthesis Circuit

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ADF4213BCP-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：CSP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：5A991.BHTS代码：8542.39.00.01
风险等级：5.76模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N20JESD-609代码：e0
长度：4 mm湿度敏感等级：3
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：VQCCN
封装等效代码：LCC20,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
座面最大高度：0.9 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：20 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

ADF4213BCP-REEL7 数据手册

 浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第2页浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第3页浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第4页浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第6页浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第7页浏览型号ADF4213BCP-REEL7的Datasheet PDF文件第8页 
ADF4210/ADF4211/ADF4212/ADF4213  
PIN FUNCTION DESCRIPTIONS  
Pin Number  
TSSOP  
Mnemonic  
DD1  
Function  
1
V
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as  
close as possible to this pin. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must have  
the same potential as VDD2.  
2
3
VP1  
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where  
V
DD1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.  
CPRF  
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input  
to an external VCO.  
4
5
6
7
8
DGNDRF  
RFIN  
AGNDRF  
FLO  
Ground Pin for the RF Digital Circuitry.  
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.  
Ground Pin for the RF Analog Circuitry.  
RF/IF Fastlock Mode.  
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input  
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.  
9
DGNDIF  
Digital Ground for the IF Digital, Interface and Control Circuitry.  
10  
MUXOUT  
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled  
Reference Frequency to be accessed externally.  
11  
CLK  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is  
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance  
CMOS input.  
12  
13  
14  
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This  
input is a high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into  
one of the four latches, the latch being selected using the control bits.  
RSET  
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output  
current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is  
13.5  
ICP MAX  
=
RSET  
So, with RSET = 2.7 kΩ, ICP MAX = 5 mA for both the RF and IF Charge Pumps.  
15  
16  
17  
18  
AGNDIF  
IFIN  
DGNDIF  
CPIF  
Ground Pin for the IF Analog Circuitry.  
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.  
Ground Pin for the IF Digital, Interface, and Control Circuitry.  
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input  
to an external VCO.  
19  
20  
VP2  
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where  
VDD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.  
Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should  
VDD  
2
be placed as close as possible to this pin. VDD2 should have a value of between 2.7 V and 5.5 V. VDD  
2
must have the same potential as VDD1.  
PIN CONFIGURATIONS  
CP-20  
TSSOP  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
2
V
1
1
2
DD  
DD  
20 19 18 17 16  
V 1  
V 2  
P
P
ADF4210/  
ADF4211/  
ADF4212/  
ADF4213  
CP  
CP  
3
RF  
RF  
CP  
IF  
1
2
3
4
5
15  
14  
13  
12  
11  
RF  
DGND  
ADF4210/  
ADF4211/  
ADF4212/  
ADF4213  
TOP VIEW  
(Not to Scale)  
IF  
DGND  
DGND  
DGND  
4
IF  
IN  
RF  
IF  
RF  
IN  
AGND  
RF  
IF  
5
IF  
IN  
IN  
AGND  
RF  
R
SET  
TOP VIEW  
(Not to Scale)  
AGND  
AGND  
6
RF  
IF  
FL  
O
LE  
R
7
FL  
SET  
O
LE  
REF  
8
6
7
8
9
10  
IN  
DGND  
IF  
DATA  
CLK  
9
10  
MUXOUT  
–5–  
REV. A  
12345678...20

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