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ADF4112BCPZ-RL7 PDF预览

ADF4112BCPZ-RL7

更新时间: 2024-01-25 05:36:45
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路射频信息通信管理
页数 文件大小 规格书
28页 428K
描述
RF PLL Frequency Synthesizers

ADF4112BCPZ-RL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:VQCCN,针数:20
Reach Compliance Code:unknown风险等级:5.42
其他特性:6-BIT SWALLOW COUNTER模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:S-CQCC-N20JESD-609代码:e3
长度:4 mm湿度敏感等级:3
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:VQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

ADF4112BCPZ-RL7 数据手册

 浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第1页浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第3页浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第4页浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第5页浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第6页浏览型号ADF4112BCPZ-RL7的Datasheet PDF文件第7页 
ADF4110/ADF4111/ADF4112/ADF4113  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Phase Frequency Detector (PFD) and Charge Pump............ 13  
Muxout and Lock Detect........................................................... 13  
Input Shift Register .................................................................... 13  
Function Latch............................................................................ 19  
Initialization Latch ..................................................................... 20  
Device Programming after Initial Power-Up ......................... 20  
Resynchronizing the Prescaler Output.................................... 21  
Applications..................................................................................... 22  
Local Oscillator for GSM Base Station Transmitter .............. 22  
Using a D/A Converter to Drive the RSET Pin......................... 23  
Shutdown Circuit ....................................................................... 23  
Wideband PLL............................................................................ 23  
Direct Conversion Modulator .................................................. 25  
Interfacing ................................................................................... 26  
PCB Design Guidelines for Chip Scale Package .................... 26  
Outline Dimensions....................................................................... 27  
Ordering Guide............................................................................... 28  
Applications....................................................................................... 1  
General Description ......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Characteristics..................................................................... 5  
Absolute Maximum Ratings............................................................ 6  
Transistor Count........................................................................... 6  
ESD Caution.................................................................................. 6  
Pin Configurations and Function Descriptions ........................... 7  
Typical Performance Characteristics ............................................. 8  
Circuit Description......................................................................... 12  
Reference Input Section............................................................. 12  
RF Input Stage............................................................................. 12  
Prescaler (P/P + 1)...................................................................... 12  
A and B Counters ....................................................................... 12  
R Counter .................................................................................... 12  
REVISION HISTORY  
1/13—Rev. E to Rev. F  
3/03—Data sheet changed from Rev. A to Rev. B.  
Changes to Table 1.............................................................................4  
Changes to Ordering Guide ...........................................................28  
Edits to Specifications.......................................................................2  
Updated OUTLINE DIMENSIONS .............................................24  
8/12—Rev. D to Rev. E  
1/01—Data sheet changed from Rev. 0 to Rev. A.  
Changed CP-20-1 to CP-20-6 ...........................................Universal  
Updated Outline Dimensions........................................................28  
Changes to Ordering Guide ...........................................................28  
Changes to DC Specifications in B Version, B Chips,  
Unit, and Test Conditions/Comments Columns .....................2  
Changes to Absolute Maximum Rating .........................................4  
Changes to FRINA Function Test .....................................................5  
Changes to Figure 8...........................................................................7  
New Graph Added—TPC 22 ...........................................................9  
Change to PD Polarity Box in Table V .........................................15  
Change to PD Polarity Box in Table VI........................................16  
Change to PD Polarity Paragraph .................................................17  
Addition of New Material  
5/12—Rev. C to Rev. D  
Changes to Figure 2...........................................................................5  
Changes to Figure 4 and Table 4......................................................7  
Updated Outline Dimensions........................................................28  
Changes to Ordering Guide ...........................................................28  
3/04—Data sheet changed from Rev. B to Rev. C.  
(PCB Design Guidelines for Chip–Scale package) ................23  
Replacement of CP-20 Outline with CP-20 [2] Outline ............24  
Updated Format..................................................................Universal  
Changes to Specifications .................................................................2  
Changes to Figure 32.......................................................................22  
Changes to the Ordering Guide.....................................................28  
Rev. F | Page 2 of 28  
 

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