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ADF4112BCP-REEL7 PDF预览

ADF4112BCP-REEL7

更新时间： 2024-02-06 07:30:39
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理
页数 文件大小 规格书
28页 437K
描述
IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, CQCC20, MO-220-VGGD, LFCSP-20, PLL or Frequency Synthesis Circuit

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ADF4112BCP-REEL7 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFN包装说明：MO-220-VGGD, LFCSP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：5A991.BHTS代码：8542.39.00.01
风险等级：5.42Is Samacsys：N
其他特性：6-BIT SWALLOW COUNTER模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-CQCC-N20JESD-609代码：e0
长度：4 mm湿度敏感等级：3
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：VQCCN
封装等效代码：LCC20,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：240
电源：3/5 V认证状态：Not Qualified
座面最大高度：1 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：7.5 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

ADF4112BCP-REEL7 数据手册

 浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第4页浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第5页浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第6页浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第8页浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第9页浏览型号ADF4112BCP-REEL7的Datasheet PDF文件第10页 
ADF4110/ADF4111/ADF4112/ADF4113  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
R
V
P
SET  
DV  
CP  
DD  
ADF4110  
ADF4111  
ADF4112  
ADF4113  
1
2
3
4
5
15  
14  
13  
CPGND  
AGND  
AGND  
MUXOUT  
LE  
ADF4110  
ADF4111  
ADF4112  
ADF4113  
MUXOUT  
LE  
CPGND  
AGND  
DATA  
DATA  
CLK  
RF  
RF  
B
A
IN  
IN  
RF  
B
12 CLK  
11  
IN  
IN  
TOP VIEW  
(Not to Scale)  
TOP VIEW  
(Not to Scale)  
RF  
A
CE  
CE  
AV  
DD  
DGND  
REF  
IN  
Figure 3. TSSOP Pin Configuration  
Figure 4. LFCSP Pin Configuration  
Table 4. Pin Function Descriptions  
TSSOP  
Pin No.  
LFCSP  
Pin No.  
Mnemonic Function  
1
19  
RSET  
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.  
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is  
23.5  
RSET  
ICPmax  
=
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.  
2
20  
CP  
Charge Pump Output. When enabled, this provides ± ±CP to the external loop filter, which in turn  
drives the external VCO.  
3
4
5
1
2, 3  
4
CPGND  
AGND  
RF±NB  
Charge Pump Ground. This is the ground return path for the charge pump.  
Analog Ground. This is the ground return path of the prescaler.  
Complementary ±nput to the RF Prescaler. This point should be decoupled to the ground plane with  
a small bypass capacitor, typically 100 pF. See Figure 29.  
6
7
5
6, 7  
RF±NA  
AVDD  
±nput to the RF Prescaler. This small-signal input is ac-coupled from the VCO.  
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog  
ground plane should be placed as close as possible to this pin. AVDD must be the same value  
as DVDD.  
8
8
REF±N  
Reference ±nput. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input  
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator,  
or can be ac-coupled.  
9
10  
9, 10  
11  
DGND  
CE  
Digital Ground.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into  
three-state mode. Taking the pin high powers up the device depending on the status of the power-  
down Bit F2.  
11  
12  
CLK  
Serial Clock ±nput. This serial clock is used to clock in the serial data to the registers. The data is  
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS  
input.  
12  
13  
14  
15  
13  
DATA  
LE  
Serial Data ±nput. The serial data is loaded MSB first with the two LSBs being the control bits. This  
input is a high impedance CMOS input.  
Load Enable, CMOS ±nput. When LE goes high, the data stored in the shift registers is loaded into  
one of the four latches; the latch is selected using the control bits.  
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference  
frequency to be accessed externally.  
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital  
ground plane should be placed as close as possible to this pin. DVDD must be the same value  
as AVDD.  
14  
15  
MUXOUT  
DVDD  
16, 17  
16  
18  
VP  
Charge Pump Power Supply. This should be greater than or equal to VDD. ±n systems where VDD is  
3 V, VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.  
Rev. C | Page 7 of 28  
 
1...45678910...28

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