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ADF4110BRU-REEL7 PDF预览

ADF4110BRU-REEL7

更新时间: 2024-01-22 22:02:34
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路射频光电二极管信息通信管理
页数 文件大小 规格书
28页 428K
描述
RF PLL Frequency Synthesizers

ADF4110BRU-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknown风险等级:5.14
Is Samacsys:N其他特性:6-BIT SWALLOW COUNTER
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:COMMERCIAL座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ADF4110BRU-REEL7 数据手册

 浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第1页浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第2页浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第3页浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第5页浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第6页浏览型号ADF4110BRU-REEL7的Datasheet PDF文件第7页 
ADF4110/ADF4111/ADF4112/ADF4113  
Data Sheet  
Parameter  
B Version  
B Chips1  
Unit  
Test Conditions/Comments  
POWER SUPPLIES  
AVDD  
DVDD  
VP  
2.7/5.5  
AVDD  
AVDD/6.0  
2.7/5.5  
AVDD  
AVDD/6.0  
V min/V max  
V min/V max  
AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.  
IDD5 (AIDD + DIDD)  
ADF4110  
ADF4111  
ADF4112  
ADF4113  
5.5  
5.5  
7.5  
11  
0.5  
1
4.5  
4.5  
6.5  
8.5  
0.5  
1
mA max  
mA max  
mA max  
mA max  
mA max  
µA typ  
4.5 mA typical.  
4.5 mA typical.  
6.5 mA typical.  
8.5 mA typical.  
TA = 25°C.  
IP  
Low Power Sleep Mode  
NOISE CHARACTERISTICS  
ADF4113 Normalized Phase Noise Floor6 −215  
Phase Noise Performance7  
−215  
dBc/Hz typ  
@ VCO output.  
ADF4110: 540 MHz Output8  
ADF4111: 900 MHz Output9  
ADF4112: 900 MHz Output9  
ADF4113: 900 MHz Output9  
ADF4111: 836 MHz Output10  
ADF4112: 1750 MHz Output11  
ADF4112: 1750 MHz Output12  
ADF4112: 1960 MHz Output13  
ADF4113: 1960 MHz Output13  
ADF4113: 3100 MHz Output14  
Spurious Signals  
−91  
−87  
−90  
−91  
−78  
−86  
−66  
−84  
−85  
−86  
−91  
−87  
−90  
−91  
−78  
−86  
−66  
−84  
−85  
−86  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 300 Hz offset and 30 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 200 Hz offset and 10 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 1 kHz offset and 200 kHz PFD frequency.  
@ 1 kHz offset and 1 MHz PFD frequency.  
ADF4110: 540 MHz Output9  
ADF4111: 900 MHz Output9  
ADF4112: 900 MHz Output9  
ADF4113: 900 MHz Output9  
ADF4111: 836 MHz Output10  
ADF4112: 1750 MHz Output11  
ADF4112: 1750 MHz Output12  
ADF4112: 1960 MHz Output13  
ADF4113: 1960 MHz Output13  
ADF4113: 3100 MHz Output14  
−97/−106  
−98/−110  
−91/−100  
−97/−106  
−98/−110  
−91/−100  
dBc typ  
dBc typ  
dBc typ  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 30 kHz/60 kHz and 30 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 10 kHz/20 kHz and 10 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 200 kHz/400 kHz and 200 kHz PFD frequency.  
@ 1 MHz/2 MHz and 1 MHz PFD frequency.  
−100/−110 −100/−110 dBc typ  
−81/−84  
−88/−90  
−65/−73  
−80/−84  
−80/−84  
−80/−82  
−81/−84  
−88/−90  
−65/−73  
−80/−84  
−80/−84  
−82/−82  
dBc typ  
dBc typ  
dBc typ  
dBc typ  
dBc typ  
dBc typ  
1The B chip specifications are given as typical values.  
2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that  
is less than this value.  
3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.  
4Guaranteed by design.  
5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.  
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider  
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.  
7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the  
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).  
8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.  
9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.  
10  
f
f
f
f
f
= 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.  
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz  
= 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.  
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz.  
= 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.  
REFIN  
REFIN  
REFIN  
REFIN  
REFIN  
11  
12  
13  
14  
Rev. F | Page 4 of 28  
 
 
 
 
 
 

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