ADF4001
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
V
SET
P
DV
CP
DD
CPGND
AGND
MUXOUT
LE
15 MUXOUT
14 LE
1
2
3
4
CPGND
AGND
AGND
ADF4001
TOP VIEW
(Not to Scale)
ADF4001
TOP VIEW
(Not to Scale)
RF
RF
B
DATA
CLK
IN
IN
13 DATA
12 CLK
11 CE
RF
B
A
IN
RF A 5
IN
AV
DD
CE
REF
DGND
IN
NOTES
1. TRANSISTOR COUNT 6425 (CMOS)
AND 50 (BIPOLAR).
NOTES
1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
2. CONNECT EXPOSED PAD TO AGND.
LFCSP
TSSOP
Table 1. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
RSET
1
19
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship
between ICP and RSET is
23.5
RSET
ICP MAX
So, with RSET = 4.7 kΩ, ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ICP to the external loop filter which,
in turn, drives the external VCO or VCXO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
6
7
5
6, 7
RFINA
AVDD
Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must have the
same value as DVDD
.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
9
10
9, 10
11
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12
13
14
15
13
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DVDD must be the
14
15
MUXOUT
DVDD
16, 17
same value as AVDD
.
16
18
EP
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems
where VDD is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
range of up to 5 V.
N/A
EPAD
Exposed Pad. The exposed pad should be connected to AGND.
Rev. B | Page 4
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