14-Channel, High-Voltage Data-
Acquisition Systems
ADES1754/ADES1755/ADES1756
Electrical Characteristics
(V
= +56V, T = T
to T
unless otherwise noted, where T
= -40°C and T
= +105°C. Typical values are at T = +25°C.
MAX A
DCIN
A
MIN
MAX
MIN
Operation is with the recommend application circuit. (Note 5))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
65
UNITS
POWER REQUIREMENTS
Supply Voltage, DCIN
V
9
V
V
DCIN
V
= V
DDL3
DDL2
V
V
,
,
DDL2
DDL3
External overdrive (>V
)
V
Supply Voltage VDDL2,
VDDL3
DDL2/3_REG
2
DDL2/3
3.3
0.1
5.5
allowed.
_REG
V
DDIO
Also used as V
in I C applications.
DDIO
DCIN Current,
Shutdown Mode
I
V
= 0V
µA
DCSHDN
SHDNL
SHDNL
V
> 1.8V, UART in idle mode; not
DCIN Current, Standby
Mode
in acquisition mode; balance switches,
test current sources, and alert interface
disabled; Note 6
I
2.2
3.1
mA
DCSTBY
DCIN Current, ADC
Acquisition Mode
DCIN Current, COMP
Acquisition Mode
DCIN Current, ADC +
COMP Acquisition Mode
All cell and auxiliary measurements
enabled, OVSAMPL[2:0] = 000b; Note 6
All cell and auxiliary measurements
enabled, OVSAMPL[2:0] = 000b; Note 6
All cell and auxiliary measurements
enabled; Note 6
I
4.2
4.6
5.4
5
mA
mA
mA
DC_ADC
I
5.5
6.4
DC_COMP
I
DC_ADCCOMP
Baud rate = 2Mbps (0% idle time
preambles mode), 200pF load on TXUP
and TXUN, TXL not active, not in
acquisition mode, BALSWEN,
CTSTEN = 0000h; Note 6
DCIN Incremental
Current, UART
Communication
I
DCCOMM_UA
RT
160
230
μA
ADC-only acquisition, all cells and
auxiliary channels enabled,
HV Current, ADC
Acquisition Mode
I
0.7
0.7
0.9
0.9
1.1
1.1
mA
HVMEAS
V
= V
+ 5.5V
HV
DCIN
COMP only acquisition, all cells and
auxiliary channels enabled,
HV Current, Comparator
Scan Mode
I
mA
µA
HVCOMP
V
= V
+ 5.5V
HV
HV
DCIN
DCIN
V
= V
+ 5.5V, n balancing
Incremental HV Current,
Cell-Balancing Mode
(n + 1) x (n + 1) x (n + 1) x
I
HVBAL
5
15.5
26
switches enabled
CELL VOLTAGE INPUTS (Cn, V
)
BLK
Unipolar mode, Note 7
0
5
V
Differential Input Range
V
V
CELLn
Bipolar mode,
Note 7
-2.5
2.5
Common-Mode Input
Range
V
Not connected to SWn inputs
0
65
CnCM
I
Not in acquisition mode, V = 65V
Cn
Input Leakage Current
-100
4.5
±10
10
100
20
nA
LKG_Cn
V
Input Resistance
R
V
= V
= 57.6V
MΩ
BLK
VBLK
BLK
DCIN
HVMUX Switch
Resistance
R
CTSTDAC[3:0] = Fh
1.7
3.3
5
kΩ
HVMUX
CELL-BALANCING INPUTS (SWn)
I
V
= 0V, V
= 5V, V
- 1 = 0V
SWn
Leakage Current
-1.0
0.5
+1.0
2.25
µA
LKG_SW
SW0
SWn
BALSWEN[n-1] = 1, I
BALSWEN[n-1] = 1, I
8
= 100mA
1.25
1.3
SWn
Resistance, SWn to
SWn-1
R
Ω
SW
= 300mA; Note
SWn
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