Datasheet > ADDI7004BBBCZ

ADDI7004BBBCZ

更新时间： 2024-02-07 02:55:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
3页	102K
描述
Quad-Channel, HD Image Signal Processor with Precision Timing Core

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ADDI7004BBBCZ 技术参数

Source Url Status Check Date：	2013-05-01 14:56:35.099	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	针数：	76
Reach Compliance Code：	compliant	风险等级：	2.15
Base Number Matches：	1

ADDI7004BBBCZ 数据手册

Quad-Channel, HD Image Signal Processor

with Precision Timing Core

Data Sheet

ADDI7004

FEATURES

GENERAL DESCRIPTION

Support for CCD and CMOS image sensors

4 AFE channels

1.8 V analog and digital core supply voltage

The ADDI7004 is a highly integrated, quad-channel, HD image

signal processor for high speed imaging applications. Each channel

is specified at pixel rates of up to 72 MHz and consists of a complete

Serial data output with reduced range LVDS outputs

Differential analog inputs

CDS or SHA configuration (CDS bypass) with

−3 dB, 0 dB, +3 dB, and +6 dB gain

6 dB to 42 dB, 10-bit variable gain amplifier (VGA)

14-bit, 72 MHz analog-to-digital converter (ADC)

Black level clamp with variable level control

Precision Timing core with 220 ps resolution at 72 MHz

analog front end (AFE) with ADC conversion. The Precision

Timing™ core allows adjustment of the correlated double sampler

(CDS) and sample-and-hold amplifier (SHA) clocks with 220 ps

resolution at 72 MHz operation. The ADDI7004 also contains

a reduced range low voltage differential signaling (LVDS) inter-

face for the dual-channel data outputs.

Each analog front end includes black level clamping, a CDS/SHA,

a VGA, and a 72 MHz, 14-bit analog-to-digital converter (ADC).

Operation is programmed using a 3-wire serial interface.

APPLICATIONS

Digital video cameras

Digital still cameras

Medical Imaging

Packaged in a space-saving, 6 mm × 6 mm, 76-ball BGA, the

ADDI7004 is specified over an operating temperature range of

−40°C to +85°C.

High speed industrial cameras

FUNCTIONAL BLOCK DIAGRAM

ADDI7004

DOUT0P

VREF

DOUT0N

DOUT1P

AFE1

INP_A

INM_A

CDS/

SHA

ADC

VGA

6dB ~ 42dB

DOUT1N

DOUT2P

DOUT2N

DOUT3P

DOUT3N

–3dB, 0dB, +3dB, +6dB

CLAMP

TCLK0P

INP_B

INM_B

INP_C

INM_C

INP_D

INM_D

REDUCED

AFE2

TCLK0N

TCLK1P

TCLK1N

DOUT4P

DOUT4N

DOUT5P

DOUT5N

DOUT6P

DOUT6N

DOUT7P

DOUT7N

RANGE

LVDS

INTERFACE

AFE3

AFE4

INTERNAL CLOCKS

Precision

Timing

CORE

SHP

SHD

CLI

CLPOB

PBLK

DCR

RSTB

SYNC

GENERATOR

INTERNAL

REGISTERS

SCK

SDATA

NOTES

1. THE CIRCUITRY FOR AFE1 TO AFE4 IS IDENTICAL.

Figure 1.

For more information on the ADDI7004, email Analog Devices, Inc., at afe.ccd@analog.com.

Rev. SpE

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3

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