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ADDI7006BSUZRL PDF预览

ADDI7006BSUZRL

更新时间: 2024-02-23 20:07:23
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
3页 93K
描述
6-Channel, 10-Bit, 40MSPS CCD Signal Processor

ADDI7006BSUZRL 技术参数

Source Url Status Check Date:2013-05-01 14:56:35.101是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
包装说明:TQFP-80针数:80
Reach Compliance Code:compliant风险等级:5.58
转换器类型:A/D CONVERTERJESD-30 代码:X-PQFP-G80
模拟输入通道数量:6位数:10
功能数量:1端子数量:80
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:unspecified封装形式:FLATPACK
标称供电电压:1.8 V表面贴装:YES
温度等级:OTHER端子形式:GULL WING
端子位置:QUADBase Number Matches:1

ADDI7006BSUZRL 数据手册

 浏览型号ADDI7006BSUZRL的Datasheet PDF文件第2页浏览型号ADDI7006BSUZRL的Datasheet PDF文件第3页 
6-Channel, 10-Bit, 40 MSPS  
CCD Signal Processor  
Data Sheet  
ADDI7006  
FEATURES  
GENERAL DESCRIPTION  
Six 10-bit, 40 MHz analog front-end (AFE) channels  
1.8 V analog and digital core supply voltage  
Serial data link with reduced range low voltage differential  
signaling (LVDS) outputs  
Input amplifier with −3 dB, 0 dB, +3 dB, or +6 dB gain  
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)  
Black level clamp with variable level control  
Low power consumption  
The ADDI7006 is a highly integrated 6-channel charged-coupled  
device (CCD) signal processor for high speed scanner  
applications. Each channel is specified at pixel rates of up to 40  
MHz, and consists of six complete analog front ends with  
correlated double sampling, variable gain amplification, and 10-  
bit analog-to-digital conversion. The ADDI7006 also contains a  
reduced range LVDS interface for the digital data output to  
reduce electromagnetic interference (EMI) concerns.  
Each analog front end includes black level clamping, a VGA,  
and a 40 MSPS, 10-bit analog-to-digital converter (ADC).  
Operation is programmed using a 3-wire serial interface.  
APPLICATIONS  
Digital copiers  
Multifunction copiers  
Industrial high speed scanners  
Packaged in a space-saving 80-lead TQFP package, the  
ADDI7006 is specified over an operating temperature range of  
−25°C to +85°C.  
FUNCTIONAL BLOCK DIAGRAM  
ADDI7006  
DOUT1P_A  
DOUT1N_A  
AFE1  
REP  
REM  
DOUT1P_B  
DOUT1N_B  
TCLK1P  
SHA  
ADC  
VGA  
6dB ~ 42dB  
–3dB, 0dB, +3dB, +6dB  
CLAMP  
TCLK1N  
DOUT1P_C  
DOUT1N_C  
DOUT2P_A  
DOUT2N_A  
TCLK2P  
ROP  
ROM  
GEP  
GEM  
GOP  
GOM  
BEP  
REDUCED  
RANGE  
AFE2  
LVDS  
INTERFACE  
AFE3  
AFE4  
AFE5  
TCLK2N  
DOUT2P_B  
DOUT2N_B  
DOUT2P_C  
DOUT2N_C  
BEM  
BOP  
BOM  
AFE6  
INTERNAL CLOCKS  
SHP  
SHD  
Precision  
Timing  
CORE  
CLPOB  
DCR  
CLI  
RST  
INTERNAL  
REGISTERS  
5
GPI1 TO GPI5  
SL  
SCK SCK  
SDATA  
NOTES  
1. THE CIRCUITRY FOR AFE1 TO AFE6 IS IDENTICAL.  
Figure 1.  
For more information on the ADDI7006, email Analog Devices, Inc., at afe.ccd@analog.  
Rev. SpA  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  

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