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ADCMP606BKSZ-R2 PDF预览

ADCMP606BKSZ-R2

更新时间： 2024-02-23 16:47:56
品牌 Logo 应用领域
亚德诺 - ADI 放大器光电二极管
页数 文件大小 规格书
16页 355K
描述
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators

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ADCMP606BKSZ-R2 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP6,.08针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.62
Samacsys Description：Analog Devices ADCMP606BKSZ-R2 Comparator, CML O/P, 0.0021μs 2.5 → 5.5 V 6-Pin SC-70放大器类型：COMPARATOR
最大平均偏置电流 (IIB)：5 µA25C 时的最大偏置电流 (IIB)：5 µA
最大输入失调电压：5000 µVJESD-30 代码：R-PDSO-G6
JESD-609代码：e4长度：2 mm
湿度敏感等级：1功能数量：1
端子数量：6最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified标称响应时间：2.1 ns
座面最大高度：1.1 mm子类别：Comparator
最大压摆率：26 mA供电电压上限：6 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：BIPOLAR温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：1.25 mm

ADCMP606BKSZ-R2 数据手册

 浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第2页浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第3页浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第4页浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第6页浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第7页浏览型号ADCMP606BKSZ-R2的Datasheet PDF文件第8页 
ADCMP606/ADCMP607  
TIMING INFORMATION  
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.  
1.1V  
LATCH ENABLE  
tS  
tPL  
tH  
V
IN  
DIFFERENTIAL  
INPUT VOLTAGE  
V
± V  
OS  
N
V
OD  
tPDL  
tPLOH  
Q OUTPUT  
50%  
50%  
tF  
tPDH  
Q OUTPUT  
tPLOL  
tR  
Figure 2. System Timing Diagram  
Table 2. Timing Descriptions  
Symbol Timing  
Description  
tF  
Output fall time  
Amount of time required to transition from a high to a low output as measured at the 20%  
and 80% points.  
tH  
Minimum hold time  
Minimum time after the negative transition of the latch enable signal that the input signal  
must remain unchanged to be acquired and held at the outputs.  
tPDH  
tPDL  
Input to output high delay  
Input to output low delay  
Propagation delay measured from the time the input signal crosses the reference ( the  
input offset voltage) to the 50% point of an output low-to-high transition.  
Propagation delay measured from the time the input signal crosses the reference ( the  
input offset voltage) to the 50% point of an output high-to-low transition.  
tPL  
tPLOH  
Minimum latch enable pulse width  
Latch enable to output high delay  
Minimum time that the latch enable signal must be high to acquire an input signal change.  
Propagation delay measured from the 50% point of the latch enable signal low-to-high  
transition to the 50% point of an output low-to-high transition.  
tPLOL  
tR  
Latch enable to output low delay  
Output rise time  
Propagation delay measured from the 50% point of the latch enable signal low-to-high  
transition to the 50% point of an output high-to-low transition.  
Amount of time required to transition from a low to a high output as measured at the 20%  
and 80% points.  
tS  
Minimum setup time  
Voltage overdrive  
Minimum time before the negative transition of the latch enable signal occurs that an  
input signal change must be present to be acquired and held at the outputs.  
Difference between the input voltages VA and VB.  
VOD  
Rev. 0 | Page 5 of 16  
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