Datasheet > ADCMP606_07

ADCMP606_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	371K
描述
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ADCMP606_07 数据手册

ADCMP606/ADCMP607

TIMING INFORMATION

Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

t_S

t_PL

t_H

DIFFERENTIAL

INPUT VOLTAGE

± V

t_PDL

t_PLOH

Q OUTPUT

50%

t_F

t_PDH

Q OUTPUT

t_PLOL

t_R

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing

Description

t_F

Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

t_H

Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs.

t_PDH

t_PDL

t_PL

Input to output high delay

Input to output low delay

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output low-to-high transition.

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output high-to-low transition.

Minimum time that the latch enable signal must be high to acquire an input signal

change.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

Minimum latch enable pulse width

Latch enable to output high delay

Latch enable to output low delay

Output rise time

t_PLOH

t_PLOL

t_R

t_S

Minimum setup time

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.

V_OD

Voltage overdrive

Difference between the input voltages V_Aand V_B.

Rev. A | Page 5 of 16

1 2 3 456 7 8...16

下载PDF

与ADCMP606_07相关器件

型号	品牌	描述	获取价格	数据表
ADCMP606_15	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V	获取价格
ADCMP606BKSZ-R2	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators	获取价格
ADCMP606BKSZ-REEL7	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators	获取价格
ADCMP606BKSZ-RL	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators	获取价格
ADCMP607	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators	获取价格
ADCMP607_15	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V	获取价格