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ADCMP582_15 PDF预览

ADCMP582_15

更新时间: 2024-02-16 13:07:31
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亚德诺 - ADI /
页数 文件大小 规格书
16页 430K
描述
Ultrafast SiGe Voltage Comparators

ADCMP582_15 数据手册

 浏览型号ADCMP582_15的Datasheet PDF文件第8页浏览型号ADCMP582_15的Datasheet PDF文件第9页浏览型号ADCMP582_15的Datasheet PDF文件第10页浏览型号ADCMP582_15的Datasheet PDF文件第12页浏览型号ADCMP582_15的Datasheet PDF文件第13页浏览型号ADCMP582_15的Datasheet PDF文件第14页 
ADCMP580/ADCMP581/ADCMP582  
APPLICATION INFORMATION  
GND  
POWER/GROUND LAYOUT AND BYPASSING  
The ADCMP58x family of comparators is designed for very  
high speed applications. Consequently, high speed design  
techniques must be used to achieve the specified performance.  
It is critically important to use low impedance supply planes,  
particularly for the negative supply (ꢀEE), the output supply  
plane (ꢀCCO), and the ground plane (GND). Individual supply  
planes are recommended as part of a multilayer board. Provid-  
ing the lowest inductance return path for the switching currents  
ensures the best possible performance in the target application.  
50  
50Ω  
Q
Q
16mA  
It is also important to adequately bypass the input and output  
supplies. A 1 μF electrolytic bypass capacitor should be placed  
within several inches of each power supply pin to ground. In  
addition, multiple high quality 0.1 μF bypass capacitors should  
be placed as close as possible to each of the ꢀEE, ꢀCCI, and ꢀCCO  
supply pins and should be connected to the GND plane with  
redundant vias. High frequency bypass capacitors should be  
carefully selected for minimum inductance and ESR. Parasitic  
layout inductance should be strictly avoided to maximize the  
effectiveness of the bypass at high frequencies.  
V
EE  
Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage  
GND/V  
CCO  
Q
Q
ADCMP58x FAMILY OF OUTPUT STAGES  
Specified propagation delay dispersion performance is achieved  
by using proper transmission line terminations. The outputs of  
the ADCMP580 family comparators are designed to directly  
drive 400 mꢀ into 50 Ω cable or microstrip/stripline transmis-  
sion lines terminated with 50 Ω referenced to the proper return.  
The CML output stage for the ADCMP580 is shown in the  
simplified schematic diagram in Figure 24. Each output is  
back-terminated with 50 Ω for best transmission line matching.  
The outputs of the ADCMP581/ADCMP582 are illustrated in  
Figure 25; they should be terminated to −2 ꢀ for ECL outputs of  
ADCMP581 and ꢀCCO − 2 ꢀ for PECL outputs of ADCMP582.  
As an alternative, Thevenin equivalent termination networks  
can also be used. If these high speed signals must be routed  
more than a centimeter, either microstrip or stripline techniques  
are required to ensure proper transition times and to prevent  
excessive output ringing and pulse width-dependent propagation  
delay dispersion.  
V
EE  
Figure 25. Simplified Schematic Diagram of the  
ADCMP581/ADCMP582 ECL/PECL Output Stage  
USING/DISABLING THE LATCH FEATURE  
LE  
The latch inputs (LE/ ) are active low for latch mode and are  
internally terminated with 50 Ω resistors to the ꢀTT pin. When  
using the ADCMP580, ꢀTT should be connected to ground.  
When using the ADCMP581, ꢀTT should be connected to −2 .  
When using the ADCMP582, ꢀTT should be connected externally  
to ꢀCCO − 2 , preferably with its own low inductance plane.  
When using the ADCMP580, the latch function can be disabled  
LE  
by connecting the  
pin to ꢀEE with an external pull-down  
resistor and by leaving the LE pin to ground. To prevent excessive  
power dissipation, the resistor should be 1 kΩ for the ADCMP580.  
When using the ADCMP581 comparators, the latch can be  
LE  
disabled by connecting the  
pin to ꢀEE with an external 750 Ω  
resistor and leaving the LE pin connected to −2 . The idea is to  
create an approximate 0.5 ꢀ offset using the internal resistor as  
half of the voltage divider. The ꢀTT pin should be connected as  
recommended.  
Rev. A | Page 11 of 16  
 
 
 

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