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ADC32RF80, ADC32RF83
SBAS774A –MAY 2016–REVISED DECEMBER 2016
ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
1 Features
3 Description
The ADC32RF8x (ADC32RF80 and ADC32RF83) is
a 14-bit, 3-GSPS, dual-channel telecom receiver and
feedback device family that supports RF sampling
with input frequencies up to 4 GHz and beyond.
Designed for high signal-to-noise ratio (SNR), the
ADC32RF8x family delivers a noise spectral density
of –155 dBFS/Hz as well as dynamic range and
channel isolation over a large input frequency range.
The buffered analog input with on-chip termination
provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold
glitch energy.
1
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14-Bit, Dual-Channel, 3-GSPS ADC
Noise Floor: –155 dBFS/Hz
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•
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RF Input Supports Up to 4.0 GHz
Aperture Jitter: 90 fS
Channel Isolation: 95 dB at fIN = 1.8 GHz
Spectral Performance (fIN = 900 MHz, –2 dBFS):
–
–
–
SNR: 60.1 dBFS
SFDR: 66-dBc HD2, HD3
SFDR: 76-dBc Worst Spur
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Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
Each channel can be connected to a dual-band,
digital down-converter (DDC) with up to three
independent, 16-bit numerically-controlled oscillators
(NCOs) per DDC for phase-coherent frequency
hopping. Additionally, the ADC is equipped with front-
end peak and RMS power detectors and alarm
functions to support external automatic gain control
(AGC) algorithms.
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–
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SNR: 58.9 dBFS
SFDR: 67-dBc HD2, HD3
SFDR: 76-dBc Worst Spur
On-Chip Digital Down-Converters:
–
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Up to 4 DDCs (Dual-Band Mode)
Up to 3 Independent NCOs per DDC
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On-Chip Input Clamp for Overvoltage Protection
The ADC32RF8x supports the JESD204B serial
interface with subclass 1-based deterministic latency
using data rates up to 12.5 Gbps with up to four lanes
per ADC. The device is offered in a 72-pin VQFN
package (10 mm × 10 mm) and supports the
industrial temperature range (–40°C to +85°C).
Programmable On-Chip Power Detectors with
Alarm Pins for AGC Support
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On-Chip Dither
On-Chip Input Termination
Input Full-Scale: 1.35 VPP
Support for Multi-Chip Synchronization
JESD204B Interface:
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC32RF8x
VQFN (72)
10.00 mm × 10.00 mm
–
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Subclass 1-Based Deterministic Latency
4 Lanes Per Channel at 12.5 Gbps
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
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Power Dissipation: 3.2 W/Ch at 3.0 GSPS
72-Pin VQFN Package (10 mm × 10 mm)
Simplified Block Diagram
2 Applications
Buffer
DA[0,1]P/M
DA[2,3]P/M
Digital Block
N
N
50 ꢀ
!5/
!5/
ADC
!5/
Interleave
Correction
INAP/M
•
Multi-Carrier GSM Cellular Infrastructure Base
Stations
FAST
DET.
NCO
NCO
•
•
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Telecommunications Receivers
DPD Observation Receivers
NCO
CTRL
GPIO1..4
CLKINP/M
SYSREFP/M
SYNCBP/M
PLL
Backhaul Receivers
NCO
RF Repeaters and Distributed Antenna Systems
FAST
DET.
0º/180º
Clock
NCO
N
N
Buffer
DB[0,1]P/M
DB[2,3]P/M
Digital Block
!5/
!5/
!5/
Interleave
Correction
ADC
INBP/M
50 ꢀ
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.