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ADC104S051CIMMX/NOPB PDF预览

ADC104S051CIMMX/NOPB

更新时间: 2024-02-28 15:34:52
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
25页 1307K
描述
ADC104S051 4 Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter

ADC104S051CIMMX/NOPB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP10,.19,20
针数:10Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.41
最大模拟输入电压:5.25 V最小模拟输入电压:
最长转换时间:4.0625 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:S-PDSO-G10JESD-609代码:e3
长度:3 mm最大线性误差 (EL):0.0586%
湿度敏感等级:1模拟输入通道数量:4
位数:10功能数量:1
端子数量:10最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY
输出格式:SERIAL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified采样速率:0.5 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:1.1 mm
子类别:Analog to Digital Converters标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm

ADC104S051CIMMX/NOPB 数据手册

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ADC104S051  
www.ti.com  
SNAS253G NOVEMBER 2004REVISED MARCH 2013  
Figure 2. Timing Test Circuit  
CS  
t
t
CONVERT  
ACQ  
2
tCH  
SCLK  
1
3
4
5
6
7
8
13  
14  
15  
16  
t
EN  
t
DIS  
t
ACC  
t
CL  
Tri-State  
DOUT  
DIN  
Z3  
Z2  
Z1  
Z0  
DB9  
DB8  
DB7  
DB6  
DB1  
DB0  
Zero  
Zero  
t
H
t
SU  
DONTC  
DONT DONTC ADD2 ADD1 ADD0  
DONTC DONTC  
Figure 3. ADC104S051 Serial Timing Diagram  
CS  
t
CSU  
SCLK  
SCLK  
t
CLH  
Figure 4. SCLK and CS Timing Parameters  
Specification Definitions  
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold  
capacitor to charge up to the input voltage.  
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the  
input signal is acquired or held for conversion.  
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input  
voltage to a digital word.  
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy  
from one analog input that appears at the measured analog input.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB.  
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The  
specification here refers to the SCLK.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise  
and Distortion or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to  
a perfect ADC of this (ENOB) number of bits.  
Copyright © 2004–2013, Texas Instruments Incorporated  
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