Datasheet > ADC104S021Q-Q1

ADC104S021Q-Q1

更新时间： 2023-09-03 20:30:48

品牌	Logo	应用领域
德州仪器 - TI		转换器模数转换器
页数	文件大小	规格书
29页	1164K
描述
汽车类、4 通道、50ksps 至 200ksps、10 位模数转换器

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ADC104S021Q-Q1 数据手册

ADC104S021

www.ti.com

SNAS278H –FEBRUARY 2005–REVISED MARCH 2013

ADC104S021/ADC104S021Q Converter Electrical Characteristics ⁽¹⁾⁽²⁾(continued)

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, unless otherwise noted. Boldface limits apply for T_A= T_MINto T_MAX; all other limits T_A= 25°C.

(3)

Symbol

Parameter

Conditions

Typical

±0.01

Limits

Units

I_OZH, I_OZLTRI-STATE® Leakage Current

±1

µA (max)

pF (max)

C_OUT

TRI-STATE® Output Capacitance

Output Coding

Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (C_L= 10 pF)

2.7

V (min)

V_A

Supply Voltage

5.25

V (max)

V_A= +5.25V,

f_SAMPLE= 200 ksps, f_IN= 40 kHz

1.3

0.55

1.8

0.7

mA (max)

Supply Current, Normal Mode

(Operational, CS low)

V_A= +3.6V,

f_SAMPLE= 200 ksps, f_IN= 40 kHz

mA (max)

I_A

V_A= +5.25V,

f_SAMPLE= 0 ksps

Supply Current, Shutdown (CS high)

V_A= +3.6V,

f_SAMPLE= 0 ksps

V_A= +5.25V

V_A= +3.6V

V_A= +5.25V

V_A= +3.6V

6.9

9.5

2.5

mW (max)

µW

Power Consumption, Normal Mode

(Operational, CS low)

1.94

0.47

0.12

P_D

Power Consumption, Shutdown (CS

high)

µW

AC ELECTRICAL CHARACTERISTICS

0.8

3.2

200

MHz (min)

MHz (max)

ksps (min)

ksps (max)

SCLK cycles

% (min)

(4)

f_SCLK

Clock Frequency

f_S

Sample Rate

t_CONV

Conversion Time

SCLK Duty Cycle

f_SCLK= 3.2 MHz

% (max)

t_ACQ

Track/Hold Acquisition Time

Throughput Time

Full-Scale Step Input

SCLK cycles

Acquisition Time + Conversion Time

(4) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is

specified under Operating Ratings.

ADC104S021/ADC104S021Q Timing Specifications⁽¹⁾

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 0.8 MHz to 3.2 MHz, f_SAMPLE= 50

ksps to 200 ksps, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

(2)

Symbol

Parameter

Conditions

V_A= +3.0V

Typical

−3.5

−0.5

+4.5

+1.5

Limits

Units

(3)

t_CSU

Setup Time SCLK High to CS Falling Edge

ns (min)

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

t_CLH

Hold time SCLK Low to CS Falling Edge

Delay from CS Until DOUT active

ns (min)

ns (max)

t_EN

+16.5

+15

t_ACC

t_SU

Data Access Time after SCLK Falling Edge

Data Setup Time Prior to SCLK Rising Edge

ns (max)

ns (min)

(1) PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas

Instruments upon request.

(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(3) Clock may be either high or low when CS is asserted as long as setup and hold times t_CSUand t_CLHare strictly observed.

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