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ADC104S021CIMM PDF预览

ADC104S021CIMM

更新时间: 2024-02-10 11:41:02
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
19页 918K
描述
4 Channel, 200 kSPS, 10-Bit A/D Converter

ADC104S021CIMM 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.72转换器类型:ADC, SUCCESSIVE APPROXIMATION
输出位码:OFFSET BINARYBase Number Matches:1

ADC104S021CIMM 数据手册

 浏览型号ADC104S021CIMM的Datasheet PDF文件第2页浏览型号ADC104S021CIMM的Datasheet PDF文件第3页浏览型号ADC104S021CIMM的Datasheet PDF文件第4页浏览型号ADC104S021CIMM的Datasheet PDF文件第6页浏览型号ADC104S021CIMM的Datasheet PDF文件第7页浏览型号ADC104S021CIMM的Datasheet PDF文件第8页 
ADC104S021 Timing Specifications  
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz,  
fSAMPLE = 50 kSPS to 200 kSPS, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.  
Limits  
(Note 7)  
Symbol  
tCSU  
Parameter  
Conditions  
VA = +3.0V  
Typical  
Units  
−3.5  
−0.5  
+4.5  
+1.5  
+4  
Setup Time SCLK High to CS Falling Edge  
Hold time SCLK Low to CS Falling Edge  
Delay from CS Until DOUT active  
(Note 10)  
(Note 10)  
10  
10  
30  
30  
ns (min)  
ns (min)  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
tCLH  
ns  
tEN  
(max)  
+2  
+16.5  
+15  
+3  
ns  
tACC  
Data Access Time after SCLK Falling Edge  
(max)  
tSU  
tH  
Data Setup Time Prior to SCLK Rising Edge  
Data Valid SCLK Hold Time  
10  
ns (min)  
ns (min)  
+3  
10  
0.5 x  
tSCLK  
0.5 x  
tSCLK  
1.7  
0.3 x  
tSCLK  
0.3 x  
tSCLK  
tCH  
tCL  
SCLK High Pulse Width  
SCLK Low Pulse Width  
ns (min)  
ns (min)  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
Output Falling  
Output Rising  
1.2  
ns  
tDIS  
CS Rising Edge to DOUT High-Impedance  
20  
(max)  
1.0  
1.0  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions.  
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.  
<
>
V ), the current at that pin should be limited to 10 mA. The 20  
Note 3: When the input voltage at any pin exceeds the power supply (that is, V  
GND or V  
IN  
IN  
A
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute  
Maximum Rating specification does not apply to the V pin. The current into the V pin is limited by the Analog Supply Voltage specification.  
A
A
Note 4: The absolute maximum junction temperature (T max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T max, the  
J
J
junction-to-ambient thermal resistance (θ ), and the ambient temperature (T ), and can be calculated using the formula P MAX = (T max − T )/θ . The values  
JA  
A
D
J
A
JA  
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven  
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.  
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through zero ohms.  
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.  
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).  
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under  
Operating Ratings.  
Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.  
Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t  
and t  
.
CLH  
CSU  
5
www.national.com  

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