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ADBF531WBSTZ4 PDF预览

ADBF531WBSTZ4

更新时间： 2024-01-27 04:19:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
64页 2449K
描述
Blackfin Embedded Processor

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ADBF531WBSTZ4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP,针数：176
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.73
地址总线宽度：19桶式移位器：YES
边界扫描：YES最大时钟频率：40 MHz
外部数据总线宽度：16格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PQFP-G176
长度：24 mm低功率模式：YES
端子数量：176最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：1.45 V最小供电电压：0.95 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

ADBF531WBSTZ4 数据手册

 浏览型号ADBF531WBSTZ4的Datasheet PDF文件第2页浏览型号ADBF531WBSTZ4的Datasheet PDF文件第3页浏览型号ADBF531WBSTZ4的Datasheet PDF文件第4页浏览型号ADBF531WBSTZ4的Datasheet PDF文件第5页浏览型号ADBF531WBSTZ4的Datasheet PDF文件第6页浏览型号ADBF531WBSTZ4的Datasheet PDF文件第7页 
Blackfin  
Embedded Processor  
ADSP-BF531/ADSP-BF532/ADSP-BF533  
FEATURES  
PERIPHERALS  
Up to 600 MHz high performance Blackfin processor  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
RISC-like register and instruction model for ease of pro-  
gramming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
Wide range of operating voltages (see Operating Conditions  
on Page 20)  
Parallel peripheral interface PPI, supporting  
ITU-R 656 video data formats  
2 dual-channel, full duplex synchronous serial ports, sup-  
porting eight stereo I2S channels  
2 memory-to-memory DMAs  
8 peripheral DMAs  
SPI-compatible port  
Three 32-bit timer/counters with PWM support  
Real-time clock and watchdog timer  
32-bit core timer  
Qualified for Automotive Applications (see Automotive Prod-  
ucts on Page 62)  
Programmable on-chip voltage regulator  
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP  
packages  
Up to 16 general-purpose I/O pins (GPIO)  
UART with support for IrDA  
Event handler  
Debug/JTAG interface  
MEMORY  
On-chip PLL capable of frequency multiplication  
Up to 148K bytes of on-chip memory (see Table 1 on Page 3)  
Memory management unit providing memory protection  
External memory controller with glueless support for  
SDRAM, SRAM, flash, and ROM  
Flexible memory booting options from SPI and  
external memory  
JTAG TEST AND EMULATION  
VOLTAGE REGULATOR  
INTERRUPT  
CONTROLLER  
WATCHDOG  
TIMER  
B
RTC  
L1  
L1  
DATA  
MEMORY  
DMA  
CONTROLLER  
PPI  
INSTRUCTION  
MEMORY  
GPIO  
PORT  
F
TIMER0  
-2  
DMA  
EXTERNAL  
BUS  
SPI  
DMA CORE BUS  
EXTERNAL ACCESS BUS  
UART  
EXTERNAL PORT  
FLASH, SDRAM CONTROL  
SPORT0-1  
16  
BOOT ROM  
Figure 1. Functional Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. I Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
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