Datasheet > ADAU1978WBCPZ-RL

ADAU1978WBCPZ-RL

更新时间： 2022-06-07 08:33:19

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
44页	2392K
描述
Quad Analog-to-Digital Converter (ADC)

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ADAU1978WBCPZ-RL 数据手册

Data Sheet

ADAU1978

TIMING SPECIFICATIONS

Table 5.

Limit at

Min Max

Parameter

INPUT MASTER CLOCK (MCLK)

Duty Cycle

Unit

Description

MHz

MCLKIN duty cycle; MCLKIN at 256 × f_S, 384 × f_S, 512 × f_S, and 768 × f_S

MCLKIN frequency, PLL in MCLK mode

f_MCLKIN

See Table 9

RESET

Reset Pulse

RST low

PLL

Lock Time

I²C PORT

f_SCL

t_SCLH

t_SCLL

t_SCS

t_SCH

t_DS

t_DH

400

See Figure 4

SCL frequency

SCL high

SCL low

kHz

µs

0.6

1.3

0.6

100

Setup time; relevant for repeated start condition

Hold time; after this period of time, the first clock pulse is generated

Data setup time

Data hold time

t_SCR

t_SCF

t_SDR

t_SDF

300

µs

SCL rise time

SCL fall time

SDA rise time

SDA fall time

Bus-free time; time between stop and start

Setup time for stop condition

see Figure 3

CCLK frequency

CCLK high

t_BFT

1.3

0.6

t_SUSTO

SPI PORT

f_CCLK

t_CCPH

t_CCPL

t_CDS

MHz

CCLK low

CIN setup to CCLK rising

CIN hold from CCLK rising

CLATCH setup to CCLK rising

CLATCH hold from CCLK rising

CLATCH high

t_CDH

t_CLS

t_CLH

t_CLPH

t_COE

COUT enable from CLATCH falling

COUT delay from CCLK falling

COUT tristate from CLATCH rising

t_COD

t_COTS

ADC SERIAL PORT

see Figure 2

t_ABH

t_ABL

t_ALS

t_ALH

t_ABDD

BCLK high, slave mode

BCLK low, slave mode

LRCLK setup to BCLK rising, slave mode

LRCLK hold from BCLK rising, slave mode

SDATAOUTx delay from BCLK falling

Rev. 0 | Page 5 of 44

1 2 3 456 7 8...44

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