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AD9951

更新时间： 2024-01-17 11:29:49
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 789K
描述
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

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AD9951 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HTFQFP,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.6
边界扫描：NO最大时钟频率：400 MHz
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm低功率模式：YES
湿度敏感等级：3端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HTFQFP
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：1

AD9951 数据手册

 浏览型号AD9951的Datasheet PDF文件第2页浏览型号AD9951的Datasheet PDF文件第3页浏览型号AD9951的Datasheet PDF文件第4页浏览型号AD9951的Datasheet PDF文件第6页浏览型号AD9951的Datasheet PDF文件第7页浏览型号AD9951的Datasheet PDF文件第8页 
AD9951  
Parameter  
Temp Min  
Typ  
25  
2
Max  
Unit  
TIMING CHARACTERISTICS  
Serial Control Bus  
Maximum Frequency  
FULL  
Mbps  
ns  
ns  
ns  
ns  
Minimum Clock Pulse Width Low  
Minimum Clock Pulse Width High  
Maximum Clock Rise/Fall Time  
Minimum Data Setup Time DVDD_I/O = 3.3 V  
Minimum Data Setup Time DVDD_I/O = 1.8 V  
Minimum Data Hold Time  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
FULL  
7
7
3
5
0
ns  
ns  
ns  
ms  
Maximum Data Valid Time  
Wake-Up Time2  
25  
1
Minimum Reset Pulse Width High  
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V  
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V  
I/O UPDATE, SYNC_CLK Hold Time  
Latency  
5
4
6
0
SYSCLK Cycles3  
ns  
ns  
ns  
I/O UPDATE to Frequency Change Prop Delay  
I/O UPDATE to Phase Offset Change Prop Delay  
I/O UPDATE to Amplitude Change Prop Delay  
25°C  
25°C  
25°C  
24  
24  
16  
SYSCLK Cycles  
SYSCLK Cycles  
SYSCLK Cycles  
CMOS LOGIC INPUTS  
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V  
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V  
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V  
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V  
Logic 1 Current  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
1.25  
2.2  
V
V
V
V
µA  
µA  
pF  
0.6  
0.8  
12  
12  
3
2
Logic 0 Current  
Input Capacitance  
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V  
Logic 1 Voltage  
Logic 0 Voltage  
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V  
Logic 1 Voltage  
Logic 0 Voltage  
25°C  
25°C  
1.35  
2.8  
V
V
0.4  
0.4  
25°C  
25°C  
V
V
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)  
Single-Tone Mode  
Rapid Power-Down Mode  
25°C  
25°C  
25°C  
162  
150  
20  
171  
160  
27  
mW  
mW  
mW  
Full-Sleep Mode  
SYNCHRONIZATION FUNCTION4  
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)  
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)  
SYNC_CLK Alignment Resolution5  
25°C  
25°C  
25°C  
62.5  
100  
MHz  
MHz  
SYSCLK Cycles  
1
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-  
formance of the device.  
2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9951 section). The longest time required is for the  
reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values  
are used.  
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,  
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-  
quency is the same as the external reference clock frequency.  
4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.  
5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock  
edges are aligned, the synchronization function should not increase the skew between the two edges.  
Rev. 0 | Page 5 of 28  
 
 
 
 
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