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AD9889ABBCZ-80

更新时间： 2024-02-04 20:10:24

品牌	Logo	应用领域
亚德诺 - ADI		消费电路商用集成电路
页数	文件大小	规格书
12页	254K
描述
High Performance HDMI/DVI Transmitter

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AD9889ABBCZ-80 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LFBGA, BGA76,10X10,20	针数：	76
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	7.97
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PBGA-B76	JESD-609代码：	e1
长度：	6 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	76
最高工作温度：	90 °C	最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA76,10X10,20	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	子类别：	Other Consumer ICs
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	0.5 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	6 mm	Base Number Matches：	1

AD9889ABBCZ-80 数据手册

AD9889A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BOTTOM VIEW

(Not to Scale)

Figure 2. 76-Ball BGA Configuration (Top View)

Table 3. Pin Function Descriptions

Pin No.

Mnemonic Type¹Description

A1 to A10, B1

to B10, C9,

D[23:0]

Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.

C10, D9, D10

CLK

HSYNC

VSYNC

EXT_SW

HPD

Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.

Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.

Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to

5.0 V CMOS logic level.

S/PDIF

MCLK

S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips

digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.

Audio Reference Clock. 128 × N × f_Swith N = 1, 2, 3, or 4. Set to 128 × sampling frequency (f_S),

256 × f_S, 384 × f_S, or 512 × f_S. 1.8 V to 3.3 V CMOS logic level.

F2, F1, G2, G1 I²S[3:0]

I²S Audio Data Inputs. These represent the eight channels of audio (two per input) available

through I²S. Supports CMOS logic levels from 1.8 V to 3.3 V.

SCLK

LRCLK

PD/A0

I²S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.

Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.

Power-Down Control and I²C Address Selection. The I²C address and the PD polarity are set by the

PD/A0 pin state when the supplies are applied to the AD9889A. 1.8 V to 3.3 V CMOS logic level.

K1, K2

TxC−/TxC+

Tx2−/Tx2+

Tx1−/Tx1+

Tx0−/Tx0+

INT

Differential Clock Output. Differential clock output at pixel clock rate; transition minimized

differential signaling (TMDS) logic level.

Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS

logic level.

Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate;

TMDS logic level.

Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS

logic level.

K10, J10

K7, K8

K4, K5

H10

Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is

recommended.

J2, J5, J8, K9

D5, D6, D7, E7 DVDD

AVDD

1.8 V Power Supply for TMDS Outputs.

1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic

and I/Os. They should be filtered and as quiet as possible.

G4, G5, J1

PVDD

GND

1.8 V PLL Power Supply. The most sensitive portion of the AD9889A is the clock generation

circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free

power to these pins.

Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889A be

assembled on a single, solid ground plane with careful attention given to ground current paths.

D4, E4, F4, J4,

G6, J6, K6, F7,

G7, H9, J9

Rev. 0 | Page 5 of 12

1 2 3 456 7 8...12

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