Datasheet > AD9843AJST

AD9843AJST

更新时间： 2024-01-10 13:54:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	169K
描述
Complete 10-Bit 20 MSPS CCD Signal Processor

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技术参数
数据手册

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AD9843AJST 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.57
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	7 mm
Base Number Matches：	1

AD9843AJST 数据手册

AD9843A

chain at the specified gain setting. The output noise can be

converted to an equivalent voltage, using the relationship 1 LSB

= (ADC Full Scale/2^Ncodes) when N is the bit resolution of the

ADC. For the AD9843A, 1 LSB is 2 mV.

DEFINITIONS OF SPECIFICATIONS

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every code

must have a finite width. No missing codes guaranteed to 10-bit

resolution indicates that all 1024 codes, respectively, must be

present over all operating conditions.

POWER SUPPLY REJECTION (PSR)

The PSR is measured with a step change applied to the supply

pins. This represents a very high-frequency disturbance on the

AD9843A’s power supply. The PSR specification is calculated

from the change in the data outputs for a given step change in

the supply voltage.

PEAK NONLINEARITY

Peak nonlinearity, a full signal chain specification, refers to

the peak deviation of the output of the AD9843A from a true

straight line. The point used as “zero scale” occurs 1/2 LSB

before the first code transition. “Positive full scale” is defined

as a Level 1, 1/2 LSB beyond the last code transition. The devia-

tion is measured from the middle of each particular output

code to the true straight line. The error is then expressed as a

percentage of the 2 V ADC full-scale signal. The input signal is

always appropriately gained up to fill the ADC’s full-scale range.

INTERNAL DELAY FOR SHP/SHD

The internal delay (also called aperture delay) is the time delay

that occurs from when a sampling edge is applied to the AD9843A

until the actual sample of the input signal is held. Both SHP and

SHD sample the input signal during the transition from low to

high, so the internal delay is measured from each clock’s rising

edge to the instant the actual internal sample is taken.

TOTAL OUTPUT NOISE

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB, and represents the rms noise level of the total signal

EQUIVALENT INPUT CIRCUITS

DVDD

ACVDD

330ꢁ

ACVSS

DVSS

Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,

CLPDM, HD, VD, PBLK, SCK, SL

Figure 3. CCDIN (Pin 30)

DVDD

DRVDD

DATA

DVDD

DATA IN

330ꢁ

THREE-

STATE

DATA OUT

DOUT

RNW

DVSS

Figure 4. SDATA (Pin 47)

DVSS

DRVSS

Figure 2. Data Outputs

REV. 0

–7–

1...4 5 678 9 10...16

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与AD9843AJST相关器件

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AD9843AJSTRL	ROCHESTER	SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, LQFP-48	获取价格
AD9843AJSTZ	ADI	IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, LQFP-48, Consumer IC:Other	获取价格
AD9843AJSTZRL	ROCHESTER	SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, LQFP-48	获取价格
AD9843AJSTZRL	ADI	IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, LQFP-48, Consumer IC:Other	获取价格
AD9844	ADI	Complete 12-Bit 20 MSPS CCD Signal Processor	获取价格
AD9844A	ADI	Complete 12-Bit 20 MSPS CCD Signal Processor	获取价格

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