Data Sheet
AD8411A
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Parameter
Rating
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
Supply Voltage (VS to GND)
Input Voltage Range, Continuous
Common-Mode
6 V
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
+IN to GND
−20 V to +85 V
−20 V to +85 V
Field-induced robotic charged device model (FICDM) per ANSI/ES-
DA/JEDEC JS-002.
−IN to GND
Differential
+IN to −IN
± 20 V
ESD Ratings for AD8411A
VREF1, VREF
2
GND − 0.3 V to VS + 0.3 V
0.3 V
Table 4. AD8411A, 8-Lead SOIC_N
Reverse Supply Voltage
Temperature
ESD Model
Withstand Threshold (V)
Class
Operating Range
−40°C to +125°C
−65°C to +150°C
Indefinite
FICDM
±1000
C3
Storage Range
Table 5. AD8411A, 8-Lead MSOP
Output Short-Circuit Duration
ESD Model
Withstand Threshold (V)
Class
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
HBM
±4000
±1250
3A
C3
FICDM
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection, junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJB is the junction-
to-board thermal resistance. θJCT is the junction-to-case thermal
resistance.
Table 3. Thermal Resistance
Package Type1
θJA
θJB
θJCT
Unit
R-8
142.8
152
140.6
120.6
64.01
59.7
°C/W
°C/W
RM-8
1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board for θJA, JEDEC 2S2P thermal impedance with ring style cold plate
attached to PCB for θJB, and a JEDEC 1S0P thermal test board for θJCT. Refer
to JEDEC JESD-51.
analog.com
Rev. A | 6 of 25