AD8400/AD8402/AD8403–SPECIFICATIONS
All VERSIONS
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
SWITCHING CHARACTERISTICS2, 3
Input Clock Pulse Width
Data Setup Time
tCH, tCL
tDS
tDH
Clock Level High or Low
10
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
CLK to SDO Propagation Delay4
CS Setup Time
tPD
RL = 1 kΩ to +5 V, CL ≤ 20 pF
1
25
tCSS
tCSW
tRS
tCSH
tCS1
10
10
50
0
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
10
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/µs should be maintained.
4Propagation Delay depends on value of VDD, RL and CL–see applications text.
Specifications subject to change without notice.
tRS
1
1
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
RS
0
1
tS
CLK
V
DD
0
V
±1%
OUT
V
/2
DAC REGISTER LOAD
DD
±1% ERROR BAND
1
0
CS
V
DD
Figure 1c. Reset Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
V
OUT
0V
(T = +25°C, unless otherwise noted)
Figure 1a. Timing Diagram
A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance (θJA)
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W
1
0
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
tDS
tDH
1
0
SDO
(DATA OUT)
A'x OR D'x
tPD_MIN
A'x OR D'x
tPD_MAX
tCS1
tCH
1
0
1
0
CLK
tCL
tCSS
tCSH
tCSW
tS
CS
V
DD
±1 %
V
OUT
0V
±1 % ERROR BAND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 1b. Detail Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
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