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AD8370ARE-REEL7 PDF预览

AD8370ARE-REEL7

更新时间: 2024-01-22 19:10:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 1207K
描述
LF to 750 MHz Digitally Controlled VGA

AD8370ARE-REEL7 数据手册

 浏览型号AD8370ARE-REEL7的Datasheet PDF文件第1页浏览型号AD8370ARE-REEL7的Datasheet PDF文件第2页浏览型号AD8370ARE-REEL7的Datasheet PDF文件第3页浏览型号AD8370ARE-REEL7的Datasheet PDF文件第5页浏览型号AD8370ARE-REEL7的Datasheet PDF文件第6页浏览型号AD8370ARE-REEL7的Datasheet PDF文件第7页 
AD8370  
Parameter  
Conditions  
Min Typ  
Max  
Unit  
NOISE/HARMONIC PERFORMANCE (cont.)  
70 MHz  
Gain Flatness  
Noise Figure  
Second Harmonic  
Third Harmonic  
Output IP3  
Within 10 MHz of 70 MHz  
0.02  
dB  
dB  
dBc  
dBc  
dBm  
dBm  
7.2  
−65  
−62  
35  
1
VOUT = 2 V p-p  
VOUT = 2 V p-p  
1
Output 1 dB Compression Point  
140 MHz  
17  
Gain Flatness  
Within 10 MHz of 140 MHz  
0.03  
dB  
Noise Figure  
Second Harmonic  
Third Harmonic  
Output IP3  
Output 1 dB Compression Point  
190 MHz  
7.2  
−54  
−50  
33  
dB  
1
VOUT = 2 V p-p  
VOUT = 2 V p-p  
dBc  
dBc  
dBm  
dBm  
1
17  
Gain Flatness  
Within 10 MHz of 240 MHz  
0.03  
dB  
Noise Figure  
Second Harmonic  
Third Harmonic  
Output IP3  
Output 1 dB Compression Point  
240 MHz  
7.2  
−43  
−43  
33  
dB  
1
VOUT = 2 V p-p  
VOUT = 2 V p-p  
dBc  
dBc  
dBm  
dBm  
1
17  
Gain Flatness  
Within 10 MHz of 240 MHz  
0.04  
dB  
Noise Figure  
Second Harmonic  
Third Harmonic  
Output IP3  
Output 1 dB Compression Point  
380 MHz  
7.4  
–28  
–33  
32  
dB  
1
VOUT = 2 V p-p  
VOUT = 2 V p-p  
dBc  
dBc  
dBm  
dBm  
1
17  
Gain Flatness  
Within 10 MHz of 240 MHz  
0.04  
dB  
Noise Figure  
Output IP3  
Output 1 dB Compression Point  
POWER-INTERFACE  
Supply Voltage  
8.1  
27  
14  
dB  
dBm  
dBm  
3.02  
5.5  
V
PWUP High, GC = LG127, RL = , 4 seconds after power-on,  
thermal connection made to exposed paddle under device  
−40°C ≤ TA ≤ +85°C  
PWUP High, VOUT = 1 V p-p, ZL = 100 Ω reactive, GC = LG127  
(includes load current)  
Quiescent Current3  
79  
85.5  
105  
mA  
72.5  
4
vs. Temperature  
mA  
mA  
Total Supply Current  
82  
Power Down Current  
vs. Temperature4  
PWUP Low  
−40°C ≤TA ≤ +85°C  
3.7  
mA  
mA  
5
POWER UP INTERFACE  
Pin PWUP  
4
Power-Up Threshold  
Power-Down Threshold  
PWUP Input Bias Current  
GAIN CONTROL INTERFACE  
Voltage to enable the device  
Voltage to disable the device  
PWUP = 0 V  
Pins CLCK, DATA, and LTCH  
Voltage for a logic high  
Voltage for a logic low  
1.8  
1.8  
V
V
nA  
4
0.8  
400  
900  
4
VIH  
V
V
nA  
4
VIL  
0.8  
Input Bias Current  
1 Refer to Figure 20 for performance into a lighter load.  
2 See the 3 V Operation section for more information.  
3 Minimum and maximum specified limits for this parameter are guaranteed by production test.  
4 Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test.  
Rev. 0 | Page 4 of 28  
 
 
 

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