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AD8330_08

更新时间： 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
36页 1467K
描述
Low Cost, DC to 150 MHz Variable Gain Amplifier

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AD8330_08 数据手册

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AD8330  
SPECIFICATIONS  
VS = 5 V, TA = ±5°C, CL = 1± pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = Pin VMAG open circuit (0.5 V),  
OFST = 0 V, differential operation, unless otherwise noted.  
V
Table 1.  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
INPUT INTERFACE  
Full-Scale Input  
Pin INHI, Pin INLO  
VDBS = 0 V, differential drive  
VDBS = ±.5 V  
Pin-to-pin  
Either pin to COMM  
f = ± MHz, VDBS = ±.5 V; inputs ac-shorted  
±±.ꢀ  
±ꢀ.5  
800  
±ꢁ  
±6.3  
± k  
ꢀ
5
3.0  
±
V
mV  
Ω
pF  
nV/√Hz  
V
mV rms  
μV/°C  
V
Input Resistance  
Input Capacitance  
Voltage Noise Spectral Density  
Common-Mode Voltage Level  
Input Offset  
±.ꢁ k  
Pin OFST connected to Pin COMM  
Drift  
ꢁ
Permissible CM Range±  
0
VS  
Common-Mode AC Rejection  
f = ± MHz, 0.± V rms  
f = 50 MHz  
−60  
−55  
dB  
dB  
OUTPUT INTERFACE  
Small Signal –3 dB Bandwidth  
Peak Slew Rate  
Pin OPHI, Pin OPLO  
0 V < VDBS < ±.5 V  
VDBS = 0 V  
±50  
±500  
±ꢁ  
±ꢀ.5  
ꢁ.5  
MHz  
V/μs  
V
V
V
nV/√Hz  
Ω
dBc  
dBc  
Peak-to-Peak Output Swing  
±±.8  
±ꢀ  
ꢁ.ꢀ  
±ꢁ.ꢁ  
ꢁ.6  
VMAG ≥ ꢁ V (peaks are supply limited)  
Pin CNTR O/C  
f = ± MHz, VDBS = 0 V  
Common-Mode Voltage  
Voltage Noise Spectral Density  
Differential Output Impedance  
HDꢁꢁ  
6ꢁ  
Pin-to-pin  
±ꢁ0  
±50  
−6ꢁ  
−53  
±80  
VOUT = ± V p-p, f = ±0 MHz, RL = ± kΩ  
VOUT = ± V p-p, f = ±0 MHz, RL = ± kΩ  
Pin OFST  
CHPF on Pin OFST (0 V < VDBS < ±.5 V)  
CHPF = 3.3 nF, from OFST to CNTR (scales as ±/CHPF  
Pin CNTR  
HD3ꢁ  
OUTPUT OFFSET CONTROL  
AC-Coupled Offset  
High-Pass Corner Frequency  
COMMON-MODE CONTROL  
Usable Voltage Range  
Input Resistance  
±0  
±00  
mV rms  
kHz  
)
0.5  
ꢁ7  
ꢀ.5  
V
kΩ  
From Pin CNTR to VS/ꢁ  
VDBS, CMGN, and MODE pins  
CMGN connected to COMM  
CMGN O/C (VCMGN rises to 0.ꢁ V)  
Mode high or low  
0.3 V ≤ VDBS ≤ ±.ꢁ V  
VDBS = 0 V  
Flows out of Pin VDBS  
ꢀ
DECIBEL GAIN CONTROL  
Normal Voltage Range  
Elevated Range  
Gain Scaling  
Gain Linearity Error  
Absolute Gain Error  
Bias Current  
Incremental Resistance  
Gain Settling Time to 0.5 dB Error  
Mode Up/Down  
0 to ±.5  
0.ꢁ to ±.7  
30  
V
V
33  
+0.35  
+ꢁ  
mV/dB  
dB  
dB  
nA  
MΩ  
ns  
−0.35 ±0.±  
−ꢁ  
±0.5  
±00  
±00  
ꢁ50  
VDBS stepped from 0.05 V to ±.ꢀ5 V or ±.ꢀ5 V to 0.05 V  
Pin MODE  
Mode Up Logic Level  
Mode Down Logic Level  
LINEAR GAIN INTERFACE  
Peak Output Scaling, Gain vs. VMAG  
Gain Multiplication Factor vs. VMAG  
Usable Input Range  
Default Voltage  
Gain increases with VDBS, MODE = O/C  
Gain decreases with VDBS  
±.5  
3.8  
V
V
0.5  
ꢀ.ꢁ  
Pin VMAG, Pin CMGN  
See the Circuit Description section  
Gain is nominal when VMAG = 0.5 V  
ꢀ.0  
×ꢁ  
V/V  
0
0.ꢀ8  
5
0.5ꢁ  
V
V
kΩ  
MHz  
VMAG O/C  
0.5  
ꢀ
±50  
Incremental Resistance  
Bandwidth  
For VMAG ≥ 0.± V  
Rev. D | Page 3 of 36  
 
 
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