AD8323ARU

更新时间： 2024-02-11 18:30:41

品牌	Logo	应用领域
亚德诺 - ADI		驱动器有线电视功率控制
页数	文件大小	规格书
16页	278K
描述
5 V CATV Line Driver Fine Step Output Power Control

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数据手册

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AD8323ARU 数据手册

AD8323

(DATEN, CLK, SDATA, PD, SLEEP, V = 5 V: Full Temperature Range)

LOGIC INPUTS (TTL/CMOS Compatible Logic)

Parameter

Min

Typ

Max

Unit

Logic “1” Voltage

Logic “0” Voltage

2.1

5.0

0.8

Logic “1” Current (V_INH= 5 V) CLK, SDATA, DATEN

Logic “0” Current (V_INL= 0 V) CLK, SDATA, DATEN

Logic “1” Current (V_INH= 5 V) PD

Logic “0” Current (V_INL= 0 V) PD

Logic “1” Current (V_INH= 5 V) SLEEP

Logic “0” Current (V_INL= 0 V) SLEEP

–600

–250

µA

–100

190

–30

190

–30

TIMING REQUIREMENTS

(Full Temperature Range, V_CC= 5 V, T_R= T_F= 4 ns, f_CLK= 8 MHz unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Clock Pulsewidth (T_WH

Clock Period (T_C)

Setup Time SDATA vs. Clock (T_DS

Setup Time DATEN vs. Clock (T_ES

Hold Time SDATA vs. Clock (T_DH

Hold Time DATEN vs. Clock (T_EH

Input Rise and Fall Times, SDATA, DATEN, Clock (T_R, T_F)

)

16.0

32.0

5.0

15.0

5.0

)

3.0

VALID DATA WORD G1

VALID DATA WORD G2

SDATA

CLK

MSB. . . .LSB

8 CLOCK CYCLES

DATEN

GAIN TRANSFER (G1)

GAIN TRANSFER (G2)

OFF

ANALOG

OUTPUT

PEDESTAL

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

VALID DATA BIT

MSB-1

SDATA MSB

MSB-2

CLK

Figure 3. SDATA Timing

–3–

REV. 0

1 234 5 6 7...16

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