AD800/AD802
ABSO LUTE MAXIMUM RATINGS*
TH ERMAL CH ARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
θJC
θJA
Input Voltage (Pin 16 or Pin 17 to VCC
Maximum Junction T emperature
) . . . . VEE to +300 mV
SOIC Package
Cerdip Package
22°C/W
25°C/W
75°C/W
90°C/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD Rating
Use of a heatsink may be required depending on operating
environment.
GLO SSARY
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Maxim um and Minim um Specifications
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. T ypical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
Nom inal Center Fr equency
DATAOUT 50%
(PIN 2)
T his is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, CD, shorted.
CLKOUT 50%
(PIN 5)
Tr acking Range
T his is the range of input data rates over which the PLL will
remain in lock.
SETUP TIME
tSU
RECOVERED CLOCK
SKEW, tRCS
Captur e Range
T his is the range of input data rates over which the PLL can
acquire lock.
Figure 1. Recovered Clock Skew and Setup
(See Previous Page)
Static P hase Er r or
P IN D ESCRIP TIO NS
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Num ber Mnem onic
D escription
1
DATAOUT Differential Retimed Data Output
2
DAT AOUT Differential Retimed Data Output
3
VCC2
Digital Ground
4
5
6
CLKOUT
CLKOUT
VEE
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital VEE
Digital VEE
Digital Ground
D ata Tr ansition D ensity,
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
7
VEE
8
VCC1
Jitter
9
AVEE
Analog VEE
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
10
11
12
13
14
15
16
17
18
19
ASUBST
CF2
CF1
AVCC
VCC1
Analog Substrate
Loop Damping Capacitor Input
Loop Damping Capacitor Input
Analog Ground
Digital Ground
Digital VEE
Differential Data Input
Differential Data Input
Digital Substrate
Differential Frequency Acquisition
Indicator Output
VEE
O utput Jitter
DAT AIN
DATAIN
SUBST
FRAC
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter Toler ance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
20
FRAC
Differential Frequency Acquisition
Indicator Output
O RD ERING GUID E
Fractional Loop
D evice
Center Frequency Bandwidth
D escription
O perating Tem perature
P ackage O ption
AD800-45BQ
AD800-52BR
AD802-155BR 155.52 MHz
AD802-155KR 155.52 MHz
44.736 MHz
51.84 MHz
0.1%
0.1%
0.08%
0.08%
20-Pin Cerdip
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
Q-20
R-20
R-20
R-20
20-Pin Plastic SOIC
20-Pin Plastic SOIC
20-Pin Plastic SOIC
REV. B
–3–
5秒后页面跳转
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