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AD7937AR

更新时间： 2024-01-03 22:23:51
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
8页 158K
描述
LC2MOS 8+4 Loading Dual 12-Bit DAC

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中文翻译

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AD7937AR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknown风险等级：5.76
转换器类型：D/A CONVERTER输入位码：BINARY, OFFSET BINARY
输入格式：PARALLEL, 8 BITSJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：15.4 mm
湿度敏感等级：3位数：12
功能数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：2.65 mm标称安定时间 (tstl)：0.6 µs
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.5 mm
Base Number Matches：1

AD7937AR 数据手册

 浏览型号AD7937AR的Datasheet PDF文件第2页浏览型号AD7937AR的Datasheet PDF文件第3页浏览型号AD7937AR的Datasheet PDF文件第4页浏览型号AD7937AR的Datasheet PDF文件第5页浏览型号AD7937AR的Datasheet PDF文件第6页浏览型号AD7937AR的Datasheet PDF文件第7页 
LC2MOS  
(8+4) Loading Dual 12-Bit DAC  
a
AD7937  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Two 12-Bit DACs in One Package  
DAC Ladder Resistance Matching: 0.5%  
Surface-Mount Package  
V
DD  
4-Quadrant Multiplication  
Low Gain Error (3 LSB max Over Temperature)  
Byte Loading Structure  
AD7937  
DAC A MS  
DAC A LS  
INPUT REG  
INPUT REG  
4
8
Fast Interface Timing  
DAC A REGISTER  
APPLICATIONS  
UPD  
12  
Automatic Test Equipment  
Programmable Filters  
Audio Applications  
Synchro Applications  
Process Control  
I
OUTA  
DAC A  
A1  
A0  
AGNDA  
R
V
FBA  
REFA  
CONTROL  
LOGIC  
V
R
REFB  
CS  
FBB  
I
OUTB  
WR  
DAC B  
GENERAL DESCRIPTION  
AGNDB  
The AD7937 contains two 12-bit current output DACs on one  
monolithic chip. A separate reference input is provided for each  
DAC. The dual DAC saves valuable board space, and the mono-  
lithic construction ensures excellent thermal tracking. Both DACs  
are guaranteed 12-bit monotonic over the full temperature range.  
12  
CLR  
DAC B REGISTER  
4
8
DAC B LS  
INPUT REG  
DAC B MS  
INPUT REG  
The AD7937 has a 2-byte (eight LSBs, four MSBs) loading  
structure. It is designed for right-justified data format. The control  
signals for register loading are A0, A1, CS, WR, and UPD. Data  
is loaded to the input registers when CS and WR are low. To  
transfer this data to the DAC registers, UPD must be taken  
low with WR.  
DB7–DB0  
DGND  
PRODUCT HIGHLIGHTS  
1. DAC-to-DAC Matching  
Since both DACs are fabricated on the same chip, precise  
matching and tracking is inherent. Many applications that are  
not practical using two discrete DACs are now possible.  
Typical matching: 0.5%.  
Added features on the AD7937 include an asynchronous CLR  
line which is very useful in calibration routines. When this is  
taken low, all registers are cleared. The double buffering of the  
data inputs allows simultaneous update of both DACs. Also,  
each DAC has a separate AGND line. This increases the device  
versatility; for instance, one DAC may be operated with AGND  
biased while the other is connected in the standard configuration.  
2. Small Package Size  
The AD7937 is packaged in a small 24-lead SOIC.  
3. Wide Power Supply Tolerance  
The AD7937 is manufactured using the Linear Compatible  
CMOS (LC2MOS) process. It is speed compatible with most  
microprocessors and accepts TTL, 74HC, and 5 V CMOS logic  
level inputs.  
The device operates on a 5 V VDD, with 10% tolerance on  
this nominal figure. All specifications are guaranteed over  
this range.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  
12345678

中文翻译

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AD7937AR 替代型号

型号 品牌 替代类型 描述 数据表
AD7948ARSZ-B ADI

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