AD7878KPZ-REEL

更新时间： 2024-01-17 09:14:05

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	418K
描述
CMOS, Complete 12-Bit, 100kHz Sampling ADC with DSP Interface

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技术参数
数据手册

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AD7878KPZ-REEL 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
最大模拟输入电压：	3 V	转换器类型：	A/D CONVERTER
JESD-30 代码：	R-XDIP-T28	JESD-609代码：	e0
标称负供电电压：	-5 V	位数：	12
功能数量：	1	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出位码：	OFFSET 2'S COMPLEMENT, 2'S COMPLEMENT	封装主体材料：	CERAMIC
封装代码：	DIP	封装等效代码：	DIP28,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	+-5 V	认证状态：	Not Qualified
子类别：	Analog to Digital Converters	标称供电电压：	5 V
表面贴装：	NO	技术：	BICMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

AD7878KPZ-REEL 数据手册

AD7878

17 (16 read plus 1 write) operations all occur during t_LOWtime

periods, the conversion time will slip by 17 CLK IN cycles.

Therefore, if read or write operations can occur during t_LOW

periods, it means that the conversion time for the ADC can vary

from 7 µs to 9.12 µs (assuming 8 MHz CLK IN). This calcula-

tion assumes there is a slippage of one CLK IN cycle for each

read or write operation.

operation with ADD0 low accesses data from the FIFO while a

read with ADD0 high accesses data from the status/ control

INITIATING A CONVERSION

Conversion is initiated on the AD7878 by asserting the CONVST

input. This CONVST input is an asynchronous input indepen-

dent of either the ADC or DSP clocks. This is essential for applica-

tions where precise sampling in time is important. In these applica-

tions the signal sampling must occur at exactly equal intervals to

minimize errors due to sampling uncertainty or jitter. In these cases

the CONVST input is driven from a tamer or some precise clock

source. On receipt of a CONVST pulse, the AD7878 acknowl-

edges by taking the BUSY output low. This BUSY output can be

used to ensure no bus activity while the track/hold goes from track

to hold mode (see Extended Read/Write section). The CONVST

input must stay low for at least two CLK IN periods. The track/

hold amplifier switches from the track to hold mode on the rising

edge of CONVST and conversion is also initiated at this point.

The BUSY output returns high after the CONVST input goes high

and the ADC begins its successive approximation routine. Once

conversion has been initiated another conversion start should not

be attempted until the full conversion cycle has been completed.

Figure 5 shows the taming diagram for the conversion start.

Figure 6. Basic Read Operation

Basic Write Operation

A basic write operation to the AD7878 status/control register

consists of bringing CS and DMWR low with ADD0 high. In-

ternally these signals are gated with CLK IN to provide an

internal REGISTER ENABLE signal (see Figure 7). The pulse

width of this REGISTER ENABLE signal is effectively the

overlap between the CLK IN low time and the DMWR pulse.

This may result in shorter write pulse widths, data setup times

and data hold times than those given by the microprocessor.

The timing on the AD7878 timing diagram of Figure 8 is there-

fore given with respect to the internal REGISTER ENABLE

signal rather than the DMWR signal.

In applications where precise sampling is not critical, the

CONVST pulse can be generated from a microprocessor WR

or RD line gated with a decoded address (different from the

AD7878 CS address). Note that the CONVST pulse width

must be a minimum of two AD7878 CLK IN cycles.

Figure 5. Conversion Start Timing Diagram

READ/WRITE OPERATIONS

The AD7878 read/write operations consist of reading from the

FIFO memory and reading and writing from the status/control

DMWR and ADD0 logic inputs. A description of these operations

is given in the following sections. In addition to the basic read/write

operations there is an extended read/write operation. This can

occur if a read/write operation occurs during a CONVST pulse.

This extended read/write is intended for use with microproces-

sors that can be driven into a WAIT state, and the scheme is

recommended for applications where an external timer controls

the CONVST input asynchronously to the microprocessor read/

write operations.

Figure 7. DMWR Internal Logic

Basic Read Operation

Figure 6 shows the timing diagram for a basic read operation on

the AD7878. CS and DMRD going low accesses data from

either the status/control register or the FIFO memory. A read

Figure 8. Basic Write Operation

REV. A

–7–

1...4 5 678 9 10...16

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与AD7878KPZ-REEL相关器件

型号	品牌	描述	获取价格	数据表
AD7878LN	ADI	LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface	获取价格
AD7878LP	ADI	LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface	获取价格
AD7878LP	ROCHESTER	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC28, PLASTIC, LCC-28	获取价格
AD7878LPZ	ADI	CMOS, Complete 12-Bit, 100kHz Sampling ADC with DSP Interface	获取价格
AD7878LPZ	ROCHESTER	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC28, PLASTIC, LCC-28	获取价格
AD7878LPZ-REEL	ADI	CMOS, Complete 12-Bit, 100kHz Sampling ADC with DSP Interface	获取价格

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