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AD7878BQ

更新时间： 2024-02-01 21:18:34
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 418K
描述
LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface

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AD7878BQ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：not_compliant风险等级：5.92
最大模拟输入电压：3 V转换器类型：A/D CONVERTER
JESD-30 代码：R-XDIP-T28JESD-609代码：e0
标称负供电电压：-5 V位数：12
功能数量：1端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：OFFSET 2'S COMPLEMENT, 2'S COMPLEMENT封装主体材料：CERAMIC
封装代码：DIP封装等效代码：DIP28,.6
封装形状：RECTANGULAR封装形式：IN-LINE
电源：+-5 V认证状态：Not Qualified
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

AD7878BQ 数据手册

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AD7878  
PIN FUNCTION DESCRIPTION  
Pin  
Number  
Pin  
Mnemonic Function  
11  
ADD0  
Address Input. This control input determines whether the word placed on the output data bus during a read operation is a data  
word from the FIFO RAM or the contents of the status/control register. A logic low accesses the data word from Location 0 of  
the FIFO while a logic high selects the contents of the register (see Status/Control Register section).  
12  
13  
CS  
Chip Select. Active low logic input. The device is selected when this input is active.  
DMWR  
Dam Memory Write. Active low logic input. DMWR is used in conjunction with CS low and ADD0 high to write data to the  
status/control register. Corresponds to DMWR (ADSP-2100), R/W (MC68000, TMS32020), WE (TMS32010).  
14  
15  
DMRD  
BUSY  
Data Memory READ. Active low logic input. DMRD is used in conjunction with CS low to enable the three-state output buffers.  
Corresponds directly to DMRD (ADSP-2100), DEN (TMS32010).  
Active Low Logic Output. This output goes low when the ADC receives a CONVST pulse and remains low until the track/hold  
has gone into its hold mode. The three-state drivers of the AD7878 can be disabled while the BUSY signal is low (see Extended  
READ/WRITE section). This is achieved by writing a logic 0 to DB5 (DISO) of the status/control register. Writing a logic 1 to  
DB5 of the status/control register allows data to be accessed from the AD7878 while BUSY is low.  
16  
ALFL  
FIFO Almost Full. A logic low indicates that the word count (i.e., number of conversion results) in the FIFO memory has  
reached the programmed word count in the status/control register. ALFL is updated at the end of each conversion. The ALFL  
output is reset to a logic high when a word is read from the FIFO memory and the word count is less than the preprogrammed  
word count. It can also be set high by writing a logic 1 to DB7 (ENAF) of the status/control register.  
17  
DGND  
VCC  
Digital Ground. Ground reference for digital circuitry.  
18  
Digital supply voltage, +5 V ± 5%. Positive supply voltage for digital circuitry.  
Data Bit 11 (MSB). Three-state TTL output. Coding for the data words in FIFO RAM is twos complement.  
19  
DB11  
10–15  
16–19  
20  
DB10–DB5 Data Bit 10 to Data Bit 5. Three-state TTL input/outputs.  
DB4–DB1  
DB0  
Data Bit 4 to Data Bit 1. Three-state TTL outputs.  
Data Bit 0 (LSB). Three-state TTL output.  
21  
VDD  
Analog positive supply voltage, +5 V ± 5%.  
22  
AGND  
REF OUT  
Analog Ground. Ground reference for track/hold, reference and DAC.  
23  
Voltage Reference Output. The internal 3 V analog reference is provided at this pin. The external load capability of the reference  
is 500 µA.  
24  
25  
26  
VIN  
Analog Input. Analog input range is ±3 V.  
Analog negative supply voltage, –5 V ± 5%.  
VSS  
CONVST  
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.  
The CONVST input is asynchronous to CLK IN and independent of CS, DMWR and DMRD.  
27  
28  
RESET  
Reset. Active low logic input. A logic low sets the words in FIFO memory to 1000 0000 0000 and resets the ALFL output and  
status/control register.  
CLK IN  
Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark-space ratio of this clock can  
vary from 35/65 to 65/35.  
PIN CONFIGURATIONS  
PLCC  
LCCC  
DIP  
REV. A  
–4–  
1234567...16

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