AD7878
TIMING CHARACTERISTICS1
(VDD = 5 V ؎ 5%, VCC = 5 V ؎ 5%, VSS = –5 V ؎ 5%)
Limit at TMIN, TMAX Limit at TMIN, TMAX Limit at TMIN, TMAX
Parameter (L Grade)
(J, K, A, B Grades)
(S Grade)
Units
Conditions/Comments
tl
65
65
65
65
75
75
ns max CLK IN to BUSY Low Propagation Delay
ns max CLK IN to BUSY High Propagation Delay
t2
t3
t4
t5
t6
2 CLK IN Cycles
0
0
45
2 CLK IN Cycles
0
0
60
2 CLK IN Cycles
0
0
60
min
CONVST Pulse Width
ns min CS to DMRD/REGISTER ENABLE Setup Time
ns min CS to DMRD/ REGISTER ENABLE Hold Time
ns min DMRD Pulse Width
50
50
50
µs max
t7
16
0
41
5
16
0
57
5
16
0
57
5
ns min ADD0 to DMRD/REGISTER ENABLE Setup Time
ns min ADD0 to DMRD/REGISTER ENABLE Hold Time
ns min Data Access Time after DMRD
ns min Bus Relinquish Time
t82
t9
3
t10
45
45
45
ns max
t11
42
50
42
50
55
50
ns min REGISTER ENABLE Pulse Width
µs max
t12
t13
t14
20
10
41
20
10
57
30
10
57
ns min Data Valid to REGISTER ENABLE Setup Time
ns min Data Hold Time after REGISTER ENABLE
ns min Data Access Time after BUSY
2
tRESET
2 CLK IN Cycles
2 CLK IN Cycles
2 CLK IN Cycles
min
RESET Pulse Width
NOTES
1Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t9 and t14 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t10 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
V
V
CC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
DD to VCC . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
V
IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
Digital Inputs to DGND
CLK IN, DMWR, DMRD, RESET,
CS, CONVST, ADD0 . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Digital Outputs to DGND
a. High-Z to VOH
b. High-Z to VOL
Figure 1. Load Circuits for Access Time
ALFL, BUSY . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Data Pins
DB11–DB0 . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
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