AD781SQ

更新时间： 2024-02-13 14:07:33

品牌	Logo	应用领域
亚德诺 - ADI		放大器
页数	文件大小	规格书
8页	156K
描述
Complete 700 ns Sample-and-Hold Amplifier

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技术参数
数据手册

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AD781SQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	CERAMIC, DIP-8
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.33.00.01
风险等级：	5.18	最长采集时间：	0.7 µs
标称采集时间：	0.6 µs	放大器类型：	SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：	5 V	最小模拟输入电压：	-5 V
最大下降率：	1 V/s	JESD-30 代码：	R-GDIP-T8
JESD-609代码：	e0	负供电电压上限：	-15 V
标称负供电电压 (Vsup)：	-12 V	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	+-12 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	5.08 mm	子类别：	Sample and Hold Circuit
最大压摆率：	7 mA	供电电压上限：	15 V
标称供电电压 (Vsup)：	12 V	表面贴装：	NO
技术：	BICMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

AD781SQ 数据手册

AD781

D YNAMIC P ERFO RMANCE

OUT

HOLD – V ), mV

T he AD781 is compatible with 12-bit A-to-D converters in

terms of both accuracy and speed. T he fast acquisition time, fast

hold settling time and good output drive capability allow the

AD781 to be used with high speed, high resolution A-to-D

converters like the AD674 and AD7672. T he AD781’s fast

acquisition time provides high throughput rates for multichannel

data acquisition systems. T ypically, the sample and hold can

acquire a 10 V step in less than 600 ns. Figure 1 shows the

settling accuracy as a function of acquisition time.

, VOLTS

–4

–3

–2

–5

–1

HOLD MODE OFFSET

0.08

0.06

0.04

–1

GAIN ERROR

NONLINEARITY

Figure 3. Hold Mode Offset, Gain Error and Nonlinearity

For applications where it is important to obtain zero offset, the

hold mode offset may be nulled externally at the input to the

A-to-D converter. Adjustment of the offset may be accom-

plished through the A-to-D itself or by an external amplifier

with offset nulling capability (e.g., AD711). T he offset will

change less than 0.5 mV over the specified temperature range.

0.02

500

750

1000

250

ACQUISITION TIME – ns

Figure 1. V_OUTSettling vs. Acquisition Tim e

SUP P LY D ECO UP LING AND GRO UND ING

CO NSID ERATIO NS

T he hold settling determines the required time, after the hold

command is given, for the output to settle to its final specified

accuracy. T he typical settling behavior of the AD781 is shown

in Figure 2. T he settling time of the AD781 is sufficiently fast to

allow the SHA, in most cases, to directly drive an A-to-D

converter without the need for an added “start convert” delay.

As with any high speed, high resolution data acquisition system,

the power supplies should be well regulated and free from exces-

sive high frequency noise (ripple). T he supply connection to the

AD781 should also be capable of delivering transient currents to

the device. T o achieve the specified accuracy and dynamic per-

formance, decoupling capacitors must be placed directly at both

the positive and negative supply pins to common. Ceramic type

0.1 µF capacitors should be connected from V_CCand V_EEto

common.

ANALOG

P.S.

DIGITAL

P.S.

–12V

+5V

+12V

0.1µF 0.1µF

1µF

INPUTS

11 15

DIGITAL

DATA

AD781

Figure 2. Typical AD781 Hold Mode

AD674

OUTPUT

H O LD MO D E O FFSET

SIGNAL GROUND

T he dc accuracy of the AD781 is determined primarily by the

hold mode offset. T he hold mode offset refers to the difference

between the final held output voltage and the input signal at the

time the hold command is given. T he hold mode offset arises

from a voltage error introduced onto the hold capacitor by

charge injection of the internal switches. T he nominal hold

mode offset is specified for a 0 V input condition. Over the

input range of –5 V to +5 V, the AD781 is also characterized for

an effective gain error and nonlinearity of the held value, as

shown in Figure 3. As indicated by the AD781 specifications,

the hold mode offset is very stable over temperature.

Figure 4. Basic Grounding and Decoupling Diagram

T he AD781 does not provide separate analog and digital ground

leads as is the case with most A-to-D converters. T he common

pin is the single ground terminal for the device. It is the refer-

ence point for the sampled input voltage and the held output

voltage and also the digital ground return path. T he common

pin should be connected to the reference (analog) ground of the

A-to-D converter with a separate ground lead. Since the analog

and digital grounds in the AD781 are connected internally, the

–6–

REV. A

1...3 4 567 8

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